2019-08-16 05:50:08 +08:00
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/**********************************************************************
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors<EFBFBD>
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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#ifndef lpc8xx_SPI_H_
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#define lpc8xx_SPI_H_
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#include "LPC8xx.h"
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2019-08-17 19:52:06 +08:00
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#include "swm.h"
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2019-08-16 05:50:08 +08:00
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#define SPI_FLASH_CS1() (LPC_GPIO_PORT->SET[0] = 1<<P0_16) /* Use for LPC804 */
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#define SPI_FLASH_CS0() (LPC_GPIO_PORT->CLR[0] = 1<<P0_16) /* Use for LPC804 */
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#define DATA_WIDTH 8
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#define DUMMY_BYTE 0x55
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#define BUFFER_SIZE 64
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#define LPC_SPI0BAUDRate 500000
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#define SPI_CFG_ENABLE (1 << 0)
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#define SPI_CFG_MASTER (1 << 2)
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#define SPI_CFG_SLAVE (0 << 2)
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#define SPI_CFG_LSBF (1 << 3)
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#define SPI_CFG_CPHA (1 << 4)
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#define SPI_CFG_CPOL (1 << 5)
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#define SPI_CFG_MOSIDRV (1 << 6)
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#define SPI_CFG_LOOPBACK (1 << 7)
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#define SPI_CFG_SPOL (1<<8)
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//#define SPI_CFG_SPOL(s) (1 << (8 + s))
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#define SPI_DLY_PREDELAY(d) ((d) << 0)
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#define SPI_DLY_POSTDELAY(d) ((d) << 4)
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#define SPI_DLY_FRAMEDELAY(d) ((d) << 8)
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#define SPI_DLY_INTERDELAY(d) ((d) << 12)
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#define SPI_STAT_RXRDY (1 << 0)
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#define SPI_STAT_TXRDY (1 << 1)
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#define SPI_STAT_RXOVERRUN (1 << 2)
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#define SPI_STAT_TXUNDERRUN (1 << 3)
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#define SPI_STAT_SELNASSERT (1 << 4)
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#define SPI_STAT_SELNDEASSERT (1 << 5)
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#define SPI_STAT_CLKSTALL (1 << 6)
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#define SPI_STAT_ET (1 << 7)
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#define SPI_STAT_MSTIDLE (1<<8)
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#define SPI_STAT_ERROR_MASK (SPI_STAT_RXOVERRUN|SPI_STAT_TXUNDERRUN|SPI_STAT_SELNASSERT|SPI_STAT_SELNDEASSERT|SPI_STAT_CLKSTALL)
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#define SPI_RXRDYEN (1<<0)
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#define SPI_TXRDYEN (1<<1)
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#define SPI_RXOVEN (1<<2)
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#define SPI_TXUREN (1<<3)
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#define SPI_SSAEN (1<<4)
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#define SPI_SSDEN (1<<5)
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#define SPI_RXRDY (1<<0)
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#define SPI_TXRDY (1<<1)
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#define SPI_RXOV (1<<2)
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#define SPI_TXUR (1<<3)
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#define SPI_SSA (1<<4)
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#define SPI_SSD (1<<5)
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#define SPI_CTL_TXSSELN (1<<16)
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#define SPI_CTL_EOT (1<<20)
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#define SPI_CTL_EOF (1<<21)
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#define SPI_CTL_RXIGNORE (1<<22)
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#define SPI_CTL_LEN(b) (((b)-1)<<24)
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#define SPI_TXDATCTL_SSELN(s) (s << 16)
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#define SPI_TXDATCTL_EOT (1 << 20)
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#define SPI_TXDATCTL_EOF (1 << 21)
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#define SPI_TXDATCTL_RX_IGNORE (1 << 22)
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#define SPI_TXDATCTL_FSIZE(s) ((s) << 24)
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#define SPI_RXDAT_SOT (1 << 20)
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void SPI0_IRQHandler(void);
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void SPImasterWriteOnly( uint8_t *WrBuf, uint32_t WrLen );
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void SPImasterWriteRead( uint8_t *WrBuf, uint8_t *RdBuf, uint32_t WrLen );
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void SPImasterReadOnly( uint8_t *RdBuf, uint32_t RdLen );
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#endif /* lpc8xx_SPI_H_ */
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