221 lines
4.6 KiB
C
221 lines
4.6 KiB
C
/*
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* lpc8xx_syscon.h
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*
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* Created on:
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* Author:
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*/
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#include <stdint.h>
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#ifndef LPC8XX_SYSCON_H_
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#define LPC8XX_SYSCON_H_
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// SYSAHBCLKCTRL0 register bits
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#define ROM (1<<1)
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#define RAM0_1 (1<<2)
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#define FLASH (1<<4)
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#define I2C0 (1<<5)
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#define GPIO (1<<6)
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#define GPIO0 (1<<6)
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#define SWM (1<<7)
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#define WKT (1<<9)
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#define MRT (1<<10)
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#define SPI0 (1<<11)
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#define CRC (1<<13)
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#define UART0 (1<<14)
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#define UART1 (1<<15)
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#define WWDT (1<<17)
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#define IOCON (1<<18)
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#define ACMP (1<<19)
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#define GPIO1 (1<<20)
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#define I2C1 (1<<21)
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#define ADC (1<<24)
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#define CTIMER0 (1<<25)
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#define DAC0 (1<<27)
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#define GPIO_INT (1<<28)
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// SYSAHBCLKCTRL1 register bits
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#define CAPT (1<<0)
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#define PLU (1<<5)
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// SYSAHBCLKCTRL[] register bits (alternate form)
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typedef enum {
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CLK_ROM = 1 ,
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CLK_RAM0_1 ,
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CLK_FLASH = 4 ,
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CLK_I2C0 ,
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CLK_GPIO0 ,
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CLK_SWM ,
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CLK_WKT = 9 ,
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CLK_MRT ,
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CLK_SPI0 ,
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CLK_CRC = 13 ,
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CLK_UART0 ,
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CLK_UART1 ,
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CLK_WWDT = 17 ,
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CLK_IOCON ,
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CLK_ACMP ,
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CLK_I2C1 = 21 ,
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CLK_ADC = 24 ,
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CLK_CTIMER0 ,
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CLK_DAC0 = 27 ,
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CLK_GPIO_INT ,
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CLK_CAPT = 32,
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CLK_PLU = 37
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} CHIP_SYSCON_CLOCK_CTRL_T;
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// PRESETCTRL0 register bits
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#define FLASH_RST_N ~(1<<4)
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#define I2C0_RST_N ~(1<<5)
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#define GPIO0_RST_N ~(1<<6)
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#define SWM_RST_N ~(1<<7)
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#define WKT_RST_N ~(1<<9)
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#define MRT_RST_N ~(1<<10)
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#define SPI0_RST_N ~(1<<11)
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#define CRC_RST_N ~(1<<13)
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#define UART0_RST_N ~(1<<14)
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#define UART1_RST_N ~(1<<15)
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#define IOCON_RST_N ~(1<<18)
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#define ACMP_RST_N ~(1<<19)
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#define GPIO1_RST_N ~(1<<20)
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#define I2C1_RST_N ~(1<<21)
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#define ADC_RST_N ~(1<<24)
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#define CTIMER0_RST_N ~(1<<25)
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#define DAC0_RST_N ~(1<<27)
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#define GPIOINT_RST_N ~(1<<28)
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// PRESETCTRL1 register bits
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#define CAPT_RST_N ~(1<<0)
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#define FRG0_RST_N ~(1<<3)
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#define PLU_RST_N ~(1<<5)
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// PRESETCTRL[] register bits (alternate form)
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typedef enum {
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RESET_FLASH = 4 ,
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RESET_I2C0 ,
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RESET_GPIO0 ,
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RESET_SWM ,
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RESET_WKT = 9 ,
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RESET_MRT ,
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RESET_SPI0 ,
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RESET_CRC = 13 ,
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RESET_UART0 ,
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RESET_UART1 ,
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RESET_IOCON = 18,
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RESET_ACMP ,
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RESET_I2C1 = 21 ,
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RESET_ADC = 24 ,
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RESET_CTIMER0 ,
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RESET_DAC0 = 27 ,
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RESET_GPIO_INT ,
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RESET_CAPT = 32 ,
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RESET_FRG0 = 35 ,
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RESET_PLU = 37
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} CHIP_SYSCON_PERIPH_RESET_T;
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// STARTERP0 register bits
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#define PINT0_WAKEUP (1<<0)
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#define PINT1_WAKEUP (1<<1)
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#define PINT2_WAKEUP (1<<2)
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#define PINT3_WAKEUP (1<<3)
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#define PINT4_WAKEUP (1<<4)
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#define PINT5_WAKEUP (1<<5)
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#define PINT6_WAKEUP (1<<6)
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#define PINT7_WAKEUP (1<<7)
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// STARTERP1 register bits
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#define SPI0_INT_WAKEUP (1<<0)
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#define USART0_INT_WAKEUP (1<<3)
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#define USART1_INT_WAKEUP (1<<4)
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#define I2C1_INT_WAKEUP (1<<7)
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#define I2C0_INT_WAKEUP (1<<8)
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#define WWDT_INT_WAKE (1<<12)
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#define BOD_INT_WAKE (1<<13)
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#define WKT_INT_WAKEUP (1<<15)
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// PDAWAKECFG and PDRUNCFG register bits
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#define FROOUT_PD (1<<0)
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#define FRO_PD (1<<1)
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#define FLASH_PD (1<<2)
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#define BOD_PD (1<<3) // Also for PDSLEEPCFG
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#define ADC_PD (1<<4)
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#define LPOSC_PD (1<<6) // Also for PDSLEEPCFG
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#define DAC0_PD (1<<13)
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#define ACMP_PD (1<<15)
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// LPOSCCLKEN register bit field shifters
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#define WWDT_CLK_EN 0
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#define WKT_CLK_EN 1
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// BODCTRL register bit field shifters
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#define BODRSTLEV 0
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#define BODINTVAL 2
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#define BODRSTENA 4
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// Below entries are for clock select mux functions
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typedef enum {
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FCLKSEL_FRO_CLK = 0,
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FCLKSEL_MAIN_CLK = 1,
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FCLKSEL_FRG0CLK = 2,
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FCLKSEL_FRO_DIV_CLK = 4,
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FCLKSEL_OFF = 7
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} SYSCON_FCLKSEL_CLK_T;
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typedef enum {
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FCLK_TO_UART0 = 0,
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FCLK_TO_UART1 = 1,
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FCLK_TO_I2C0 = 5,
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FCLK_TO_I2C1 = 6,
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FCLK_TO_SPI0 = 9
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} SYSCON_FCLKSEL_T;
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typedef enum {
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FRGCLKSEL_FRO_CLK = 0,
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FRGCLKSEL_MAIN_CLK = 1,
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FRGCLKSEL_OFF = 3
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} SYSCON_FRGCLKSEL_T;
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typedef enum {
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CLKOUTSEL_FRO_CLK = 0,
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CLKOUTSEL_MAIN_CLK = 1,
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CLKOUTSEL_EXTERNAL_CLK = 3,
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CLKOUTSEL_LPOSC_CLK = 4,
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CLKOUTSEL_OFF = 7
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} SYSCON_CLKOUTSEL_T;
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typedef enum {
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ADCCLKSEL_FRO_CLK = 0,
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ADCCLKSEL_EXTERNAL_CLK = 1,
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ADCCLKSEL_OFF = 3
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} SYSCON_ADCCLKSEL_T;
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void Enable_Periph_Clock(uint32_t slot);
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void Disable_Periph_Clock(uint32_t slot);
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void Do_Periph_Reset(uint32_t slot);
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//void Config_Syspll(unsigned int which_clock, unsigned int pll_ctrl_value);
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void Config_Fclksel_Mux(uint32_t to_which_periph, uint32_t which_clock);
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#endif /* LPC8XX_SYSCON_H_ */
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