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issue #61

This commit is contained in:
olikraus 2016-09-29 21:08:36 +02:00
parent 993be7e319
commit f29165b4f0
8 changed files with 19 additions and 14 deletions
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2
csrc/u8g2.h
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@ -69,7 +69,7 @@
Use 16 Bit mode for any display with more than 240 pixel in one
direction.
*/
//#define U8G2_16BIT
#define U8G2_16BIT
/*
The following macro enables the HVLine speed optimization.

13
csrc/u8g2_setup.c
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@ -94,6 +94,10 @@ static void u8g2_update_dimension_common(u8g2_t *u8g2)
u8g2->pixel_buf_height = t;
t = u8g2_GetU8x8(u8g2)->display_info->tile_width;
#ifndef U8G2_16BIT
if ( t >= 32 )
t = 31;
#endif
t *= 8;
u8g2->pixel_buf_width = t;
@ -111,8 +115,17 @@ static void u8g2_update_dimension_common(u8g2_t *u8g2)
u8g2->buf_y1 = u8g2->buf_y0;
u8g2->buf_y1 += t;
#ifdef U8G2_16BIT
u8g2->width = u8g2_GetU8x8(u8g2)->display_info->pixel_width;
u8g2->height = u8g2_GetU8x8(u8g2)->display_info->pixel_height;
#else
u8g2->width = 240;
if ( u8g2_GetU8x8(u8g2)->display_info->pixel_width <= 240 )
u8g2->width = u8g2_GetU8x8(u8g2)->display_info->pixel_width;
u8g2->height = u8g2_GetU8x8(u8g2)->display_info->pixel_height;
#endif
}
void u8g2_update_dimension_r0(u8g2_t *u8g2)

8
csrc/u8x8_d_ssd1322.c
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@ -265,19 +265,11 @@ static const u8x8_display_info_t u8x8_ssd1322_256x64_display_info =
/* i2c_bus_clock_100kHz = */ 4,
/* data_setup_time_ns = */ 10,
/* write_pulse_width_ns = */ 150, /* SSD1322: cycle time is 300ns, so use 300/2 = 150 */
#ifdef U8G2_16BIT
/* tile_width = */ 32, /* 256 pixel, so we require 32 bytes for this */
#else
/* tile_width = */ 31, /* reduced to 240 pixel in 8 bit mode, looks odd, but at least something is visible */
#endif
/* tile_hight = */ 8,
/* default_x_offset = */ 0x01c, /* this is the byte offset (there are two pixel per byte with 4 bit per pixel) */
/* flipmode_x_offset = */ 0x01c,
#ifdef U8G2_16BIT
/* pixel_width = */ 256,
#else
/* pixel_width = */ 256-16,
#endif
/* pixel_height = */ 64
};

2
csrc/u8x8_u16toa.c
View File

@ -35,7 +35,7 @@
*/
#include "u8g2.h"
#include "u8x8.h"
const char *u8x8_u16toap(char * dest, uint16_t v)
{

2
csrc/u8x8_u8toa.c
View File

@ -34,7 +34,7 @@
*/
#include "u8g2.h"
#include "u8x8.h"
static const unsigned char u8x8_u8toa_tab[3] = { 100, 10, 1 } ;
const char *u8x8_u8toap(char * dest, uint8_t v)

2
sys/arduino/u8g2_page_buffer/GraphicsTest/GraphicsTest.ino
View File

@ -69,7 +69,7 @@
//U8G2_SSD1306_128X32_UNIVISION_1_SW_I2C u8g2(U8G2_R0, /* clock=*/ 21, /* data=*/ 20, /* reset=*/ U8X8_PIN_NONE); // Adafruit Feather M0 Basic Proto + FeatherWing OLED
//U8G2_SSD1306_128X32_UNIVISION_1_SW_I2C u8g2(U8G2_R0, /* clock=*/ SCL, /* data=*/ SDA, /* reset=*/ U8X8_PIN_NONE); // Adafruit Feather ESP8266/32u4 Boards + FeatherWing OLED
//U8G2_SSD1306_128X32_UNIVISION_1_HW_I2C u8g2(U8G2_R0, /* reset=*/ U8X8_PIN_NONE); // Adafruit ESP8266/32u4/ARM Boards + FeatherWing OLED
//U8G2_SSD1322_NHD_256X64_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
U8G2_SSD1322_NHD_256X64_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
//U8G2_SSD1322_NHD_256X64_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
//U8G2_SSD1325_NHD_128X64_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
//U8G2_SSD1325_NHD_128X64_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);

2
sys/arduino/u8g2_page_buffer/U8g2Logo/U8g2Logo.ino
View File

@ -68,7 +68,7 @@
//U8G2_SSD1306_128X32_UNIVISION_1_SW_I2C u8g2(U8G2_R0, /* clock=*/ 21, /* data=*/ 20, /* reset=*/ U8X8_PIN_NONE); // Adafruit Feather M0 Basic Proto + FeatherWing OLED
//U8G2_SSD1306_128X32_UNIVISION_1_SW_I2C u8g2(U8G2_R0, /* clock=*/ SCL, /* data=*/ SDA, /* reset=*/ U8X8_PIN_NONE); // Adafruit Feather ESP8266/32u4 Boards + FeatherWing OLED
//U8G2_SSD1306_128X32_UNIVISION_1_HW_I2C u8g2(U8G2_R0, /* reset=*/ U8X8_PIN_NONE); // Adafruit ESP8266/32u4/ARM Boards + FeatherWing OLED
//U8G2_SSD1322_NHD_256X64_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
U8G2_SSD1322_NHD_256X64_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
//U8G2_SSD1322_NHD_256X64_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
//U8G2_SSD1325_NHD_128X64_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
//U8G2_SSD1325_NHD_128X64_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);

2
tools/codebuild/codebuild.c
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@ -239,7 +239,7 @@ struct controller controller_list[] =
},
{
"ssd1322", 32, 8, "u8g2_ll_hvline_vertical_top_lsb", "u8x8_cad_011", "", COM_4WSPI|COM_3WSPI|COM_6800|COM_8080,
"", /* is_generate_u8g2_class= */ 1,
"Requires U8G2_16BIT (see u8g2.h)", /* is_generate_u8g2_class= */ 1,
{
{ "nhd_256x64" },
{ NULL }