From d7d38934a61924c695e8bb81d98bb9040d3647e9 Mon Sep 17 00:00:00 2001 From: olikraus Date: Sun, 16 Apr 2017 10:45:44 +0200 Subject: [PATCH] update --- sys/arm/stm32l031x6/u8g2_rtc/main.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/sys/arm/stm32l031x6/u8g2_rtc/main.c b/sys/arm/stm32l031x6/u8g2_rtc/main.c index 3db1ce84..50a33936 100644 --- a/sys/arm/stm32l031x6/u8g2_rtc/main.c +++ b/sys/arm/stm32l031x6/u8g2_rtc/main.c @@ -183,7 +183,7 @@ int main() /* real time clock enable */ RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */ - PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR */ + PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */ /* externel 32K clock source */ RCC->CSR |= RCC_CSR_LSEBYP; /* bypass oscillator */ @@ -216,7 +216,14 @@ int main() RTC->TR = 0; RTC->ISR =~ RTC_ISR_INIT; /* start RTC */ + PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR and RTC */ + RCC->APB1ENR &= ~RCC_APB1ENR_PWREN; /* disable power interface */ + + /* wake up time setup & start */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */ + PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */ + RTC->CR &=~ RTC_CR_WUTE; /* disable wakeup timer for reprogramming */ while((RTC->ISR & RTC_ISR_WUTWF) != RTC_ISR_WUTWF) ; @@ -238,7 +245,8 @@ int main() NVIC_EnableIRQ(RTC_IRQn); NVIC_SetPriority(RTC_IRQn, 0); - //PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR */ + PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR and RTC */ + RCC->APB1ENR &= ~RCC_APB1ENR_PWREN; /* disable power interface */ for(;;)