update info struct
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@ -73,8 +73,7 @@ static void u8g2_update_dimension_common(u8g2_t *u8g2)
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t *= 8;
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u8g2->pixel_buf_height = t;
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t = u8g2_GetU8x8(u8g2)->display_info->tile_width;
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t *= 8;
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t = u8g2_GetU8x8(u8g2)->display_info->pixel_width;
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u8g2->pixel_buf_width = t;
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t = u8g2->tile_curr_row;
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@ -92,8 +91,7 @@ static void u8g2_update_dimension_common(u8g2_t *u8g2)
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u8g2->buf_y1 += t;
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u8g2->width = u8g2->pixel_buf_width;
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t = u8g2_GetU8x8(u8g2)->display_info->tile_height;
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t *= 8;
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t = u8g2_GetU8x8(u8g2)->display_info->pixel_height;
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u8g2->height = t;
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}
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@ -216,6 +216,15 @@ struct u8x8_display_info_struct
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uint8_t tile_height;
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uint8_t default_x_offset; /* default x offset for the display */
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/* pixel width is not used by the u8x8 procedures */
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/* instead it will be used by the u8g2 procedure, because the pixel dimension can */
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/* not always be calculated from the tile_width/_height */
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/* the following conditions must be true: */
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/* pixel_width <= tile_width*8 */
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/* pixel_height <= tile_height*8 */
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uint16_t pixel_width;
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uint16_t pixel_height;
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};
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@ -122,7 +122,9 @@ static const u8x8_display_info_t u8x8_ssd1306_128x64_noname_display_info =
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/* write_pulse_width_ns = */ 150, /* SSD1306: cycle time is 300ns, so use 300/2 = 150 */
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/* tile_width = */ 16,
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/* tile_hight = */ 8,
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/* default_x_offset = */ 0
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/* default_x_offset = */ 0,
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/* pixel_width = */ 128,
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/* pixel_height = */ 64
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};
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uint8_t u8x8_d_ssd1306_128x64_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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@ -122,6 +122,8 @@ static const u8x8_display_info_t u8x8_uc1701_display_info =
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#else
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/* default_x_offset = */ 30,
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#endif
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/* pixel_width = */ 102,
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/* pixel_height = */ 64
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};
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uint8_t u8x8_d_uc1701_dogs102(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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@ -46,12 +46,17 @@
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This is a page buffer example.
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*/
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U8G2_SSD1306_128X64_NONAME_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_3W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_SW_I2C u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_6800 u8g2(U8G2_R0, 13, 11, 2, 3, 4, 5, 6, A4, /*enable=*/ 7, /*cs=*/ 10, /*dc=*/ 9, /*reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_8080 u8g2(U8G2_R0, 13, 11, 2, 3, 4, 5, 6, A4, /*enable=*/ 7, /*cs=*/ 10, /*dc=*/ 9, /*reset=*/ 8);
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U8G2_UC1701_DOGS102_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_UC1701_DOGS102_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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@ -46,12 +46,14 @@
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This is a page buffer example.
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*/
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U8G2_SSD1306_128X64_NONAME_1_4W_SW_SPI u8g2(U8G2_R2, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_4W_SW_SPI u8g2(U8G2_R2, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_3W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_SW_I2C u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_6800 u8g2(U8G2_R0, 13, 11, 2, 3, 4, 5, 6, A4, /*enable=*/ 7, /*cs=*/ 10, /*dc=*/ 9, /*reset=*/ 8);
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//U8G2_SSD1306_128X64_NONAME_1_8080 u8g2(U8G2_R0, 13, 11, 2, 3, 4, 5, 6, A4, /*enable=*/ 7, /*cs=*/ 10, /*dc=*/ 9, /*reset=*/ 8);
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U8G2_UC1701_DOGS102_1_4W_SW_SPI u8g2(U8G2_R2, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_UC1701_DOGS102_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//#define MINI_LOGO
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