issue #1090, device fn

This commit is contained in:
kraus 2020-01-14 16:47:11 +01:00
parent cdbfdcf72d
commit b39084bf21
1 changed files with 145 additions and 0 deletions

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@ -804,3 +804,148 @@ uint8_t u8x8_d_ssd1327_ws_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, vo
}
return 0;
}
/*=============================================*/
/*
Visonox VGM128096A4W10 128x96 COB
https://github.com/olikraus/u8g2/files/4052919/M02289_VGM128096A4W10_Y02.pdf
*/
static const u8x8_display_info_t u8x8_ssd1327_128x96_display_info =
{
/* chip_enable_level = */ 0,
/* chip_disable_level = */ 1,
/* post_chip_enable_wait_ns = */ 20,
/* pre_chip_disable_wait_ns = */ 10,
/* reset_pulse_width_ms = */ 100,
/* post_reset_wait_ms = */ 100, /**/
/* sda_setup_time_ns = */ 100, /* */
/* sck_pulse_width_ns = */ 100, /* */
/* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
/* spi_mode = */ 0, /* active high, rising edge */
/* i2c_bus_clock_100kHz = */ 1, /* use 1 instead of 4, because the SSD1327 seems to be very slow, Update 9 Aug 2019: The OLED from aliexpress supports 400kHz */
/* data_setup_time_ns = */ 40,
/* write_pulse_width_ns = */ 60,
/* tile_width = */ 16,
/* tile_hight = */ 12,
/* default_x_offset = */ 0,
/* flipmode_x_offset = */ 0,
/* pixel_width = */ 128,
/* pixel_height = */ 96
};
/* https://github.com/SeeedDocument/Grove_OLED_1.12/raw/master/resources/LY120-096096.pdf */
/* http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96 */
/* values from u8glib */
/*
Re-map setting in Graphic Display Data RAM, command 0x0a0
Bit 0: Column Address Re-map
Bit 1: Nibble Re-map
Bit 2: Horizontal/Vertical Address Increment
Bit 3: Not used, must be 0
Bit 4: COM Re-map
Bit 5: Not used, must be 0
Bit 6: COM Split Odd Even
Bit 7: Not used, must be 0
*/
/* init values from the Visionox datasheeet section 10.4 */
static const uint8_t u8x8_d_ssd1327_128x96_init_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
U8X8_CA(0x0fd, 0x012), /* unlock display, usually not required because the display is unlocked after reset */
U8X8_C(0x0ae), /* display off */
//U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */
U8X8_CA(0x0a8, 0x05f), /* multiplex ratio: 0x05f * 1/64 duty */
//U8X8_CA(0x0a8, 0x07f), /* multiplex ratio: 0x05f * 1/128duty */
U8X8_CA(0x0a1, 0x000), /* display start line */
//U8X8_CA(0x0a2, 0x04c), /* display offset, shift mapping ram counter */
U8X8_CA(0x0a2, 0x020), /* display offset, shift mapping ram counter */
U8X8_CA(0x0a0, 0x051), /* remap configuration */
U8X8_CA(0x0ab, 0x001), /* Enable internal VDD regulator (RESET) */
//U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128 */
U8X8_CA(0x081, 0x0df), /* contrast, brightness, 0..128 (0xdf as per datasheet) */
U8X8_CA(0x0b1, 0x022), /* phase length */
U8X8_CA(0x0b3, 0x050), /* set display clock divide ratio/oscillator frequency */
//? U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
//? U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
U8X8_C(0x0b9), /* use linear lookup table */
U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
U8X8_CA(0x0be, 0x005), /* VCOMH voltage */
U8X8_CA(0x0b6, 0x00a), /* second precharge */
U8X8_CA(0x0d5, 0x062), /* enable second precharge, internal vsl (bit0 = 0) */
U8X8_C(0x0a4), /* normal display mode */
U8X8_END_TRANSFER(), /* disable chip */
U8X8_END() /* end of sequence */
};
static const uint8_t u8x8_d_ssd1327_128x96_flip0_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
U8X8_CA(0x0a2, 0x020), /* display offset, shift mapping ram counter */
U8X8_CA(0x0a0, 0x051), /* remap configuration */
U8X8_END_TRANSFER(), /* disable chip */
U8X8_END() /* end of sequence */
};
static const uint8_t u8x8_d_ssd1327_128x96_flip1_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
U8X8_CA(0x0a2, 0x020), /* display offset, shift mapping ram counter */
U8X8_CA(0x0a0, 0x042), /* remap configuration */
U8X8_END_TRANSFER(), /* disable chip */
U8X8_END() /* end of sequence */
};
uint8_t u8x8_d_ssd1327_visionox_128x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
{
/* call the 96x96 procedure at the moment */
if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )
return 1;
if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
{
u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_128x96_display_info);
return 1;
}
else if ( msg == U8X8_MSG_DISPLAY_INIT )
{
u8x8_d_helper_display_init(u8x8);
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x96_init_seq);
return 1;
}
else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
{
if ( arg_int == 0 )
{
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x96_flip0_seq);
u8x8->x_offset = u8x8->display_info->default_x_offset;
}
else
{
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x96_flip1_seq);
u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
}
return 1;
}
return 0;
}