no wait multiscan
This commit is contained in:
olikraus
parent
111c7e7487
commit
b1e7cbefb0
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@ -202,7 +202,6 @@ void setRow(uint8_t r)
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/*=======================================================================*/
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#define ADC_SUB_TASK_NONE 0
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#define ADC_SUB_TASK_STOP_ADC 1
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#define ADC_SUB_TASK_ENABLE_ADC 2
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@ -213,14 +212,10 @@ void setRow(uint8_t r)
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#define ADC_SUB_STATE_ACTIVE 1
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#define ADC_SUB_STATE_DONE 2
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uint8_t adc_sub_task = ADC_SUB_TASK_NONE;
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uint8_t adc_sub_state = ADC_SUB_STATE_INIT;
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volatile uint8_t adc_sub_task = ADC_SUB_TASK_NONE;
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volatile uint8_t adc_sub_state = ADC_SUB_STATE_INIT;
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uint16_t adc_result = 0;
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int adcIsSubDone(void)
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{
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if ( adc_sub_state == ADC_SUB_STATE_DONE )
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@ -403,9 +398,10 @@ void initADC(void)
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{
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//__disable_irq();
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/* ADC Clock Enable */
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/* ADC and DMA Clock Enable */
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RCC->APB2ENR |= RCC_APB2ENR_ADCEN; /* enable ADC clock */
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RCC->AHBENR |= RCC_AHBENR_DMAEN; /* enable DMA clock */
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__NOP(); /* let us wait for some time */
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__NOP(); /* let us wait for some time */
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@ -475,7 +471,7 @@ void initADC(void)
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*/
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uint8_t adc_single_conversion_channel = 5;
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uint8_t adc_single_conversion_state = 0;
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volatile uint8_t adc_single_conversion_state = 0;
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uint16_t adc_single_conversion_result;
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int adcStartSingleConversion(uint8_t channel)
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@ -541,7 +537,7 @@ void adcExecSingleConversion(void)
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adc_single_conversion_state++;
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/* fall through */
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case 6:
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if ( adcIsSubDone() != 0 )
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if ( adcIsSubDone() == 0 )
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{
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adcExecSub();
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break;
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@ -559,7 +555,7 @@ void adcExecSingleConversion(void)
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adc_single_conversion_state++;
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/* fall through */
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case 8:
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if ( adcIsSubDone() != 0 )
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if ( adcIsSubDone() == 0 )
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{
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adcExecSub();
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break;
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@ -574,52 +570,11 @@ uint16_t getADC(uint8_t ch)
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{
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while( adcStartSingleConversion(ch) == 0)
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adcExecSingleConversion();
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if ( adc_single_conversion_state != 0 )
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while( adc_single_conversion_state != 0 )
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adcExecSingleConversion();
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return adc_single_conversion_result;
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}
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uint16_t getADC_old(uint8_t ch)
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{
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while( adcStartSubTask(ADC_SUB_TASK_STOP_ADC) == 0 )
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adcExecSub();
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while( adcIsSubDone() == 0 )
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adcExecSub();
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while( adcStartSubTask(ADC_SUB_TASK_DISABLE_ADC) == 0 )
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adcExecSub();
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while( adcIsSubDone() == 0 )
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adcExecSub();
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/* CONFIGURE ADC */
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//ADC1->CFGR1 &= ~ADC_CFGR1_EXTEN; /* software enabled conversion start */
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//ADC1->CFGR1 &= ~ADC_CFGR1_ALIGN; /* right alignment */
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ADC1->CFGR1 = ADC_CFGR1_RES_1; /* 8 bit resolution */
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//ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* Select a sampling mode of 111 (very slow)*/
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ADC1->SMPR = 0;
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while( adcStartSubTask(ADC_SUB_TASK_ENABLE_ADC) == 0 )
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adcExecSub();
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while( adcIsSubDone() == 0 )
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adcExecSub();
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ADC1->CHSELR = 1<<ch; /* Select channel (can be done also if ADC is enabled) */
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/* DO CONVERSION */
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while( adcStartSubTask(ADC_SUB_TASK_CONVERSION) == 0 )
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adcExecSub();
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while( adcIsSubDone() == 0 )
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adcExecSub();
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return adc_result;
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}
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/*
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Channel1:
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@ -632,16 +587,165 @@ uint16_t getADC_old(uint8_t ch)
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*/
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uint8_t adc_multi_conversion_channel = 6;
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volatile uint8_t adc_multi_conversion_state = 0;
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uint16_t adc_multi_conversion_count = 256;
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uint8_t *adc_multi_conversion_buffer = NULL;
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int adcStartMultiConversion(uint8_t channel, uint16_t cnt, uint8_t *buf)
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{
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if ( adc_multi_conversion_state != 0 )
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return 0;
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adc_multi_conversion_state = 1;
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adc_multi_conversion_channel = channel;
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adc_multi_conversion_count = cnt;
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adc_multi_conversion_buffer = buf;
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return 1;
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}
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void adcExecMultiConversion(void)
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{
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switch(adc_multi_conversion_state)
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{
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case 1:
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if ( adcStartSubTask(ADC_SUB_TASK_STOP_ADC) == 0 )
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{
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adcExecSub();
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break;
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}
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adc_multi_conversion_state++;
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/* fall through */
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case 2:
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if ( adcIsSubDone() == 0 )
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{
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adcExecSub();
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break;
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}
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adc_multi_conversion_state++;
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/* fall through */
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case 3:
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if ( adcStartSubTask(ADC_SUB_TASK_DISABLE_ADC) == 0 )
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{
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adcExecSub();
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break;
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}
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adc_multi_conversion_state++;
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/* fall through */
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case 4:
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if ( adcIsSubDone() == 0 )
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{
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adcExecSub();
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break;
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}
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/* CONFIGURE ADC */
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/* disable and reset to defaults */
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DMA1_Channel1->CCR = 0;
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/* defaults:
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- 8 Bit access --> ok
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- read from peripheral --> ok
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- none-circular mode --> ok
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- no increment mode --> will be changed below
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*/
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DMA1_Channel1->CNDTR = adc_multi_conversion_count; /* buffer size */
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DMA1_Channel1->CPAR = (uint32_t)&(ADC1->DR); /* source value */
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// DMA1_Channel1->CPAR = (uint32_t)&(GPIOA->ODR); /* source value */
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DMA1_Channel1->CMAR = (uint32_t)adc_multi_conversion_buffer; /* destination memory */
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DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S; /* 0000: select ADC for DMA CH 1 (this is reset default) */
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DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S; /* 0000: select ADC for DMA CH 2 (this is reset default) */
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DMA1_Channel1->CCR |= DMA_CCR_MINC; /* increment memory */
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DMA1_Channel1->CCR |= DMA_CCR_EN; /* enable */
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/*
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detect rising edge on external trigger (ADC_CFGR1_EXTEN_0)
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recive trigger from TIM2 (ADC_CFGR1_EXTSEL_1)
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8 Bit resolution (ADC_CFGR1_RES_1)
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Use DMA one shot mode and enable DMA (ADC_CFGR1_DMAEN)
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Once DMA is finished, it will disable continues mode (ADC_CFGR1_CONT)
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*/
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ADC1->CFGR1 =
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ADC_CFGR1_CONT /* continues mode */
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| ADC_CFGR1_EXTEN_0 /* rising edge */
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// | ADC_CFGR1_EXTEN_1 /* */
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| ADC_CFGR1_EXTSEL_1 /* TIM2 */
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// | ADC_CFGR1_RES_1 /* 8 Bit resolution, no value means 12 bit */
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| ADC_CFGR1_DMAEN; /* enable generation of DMA requests */
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//ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2;
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//ADC1->SMPR = ADC_SMPR_SMP_1 ;
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//ADC1->SMPR = ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 ;
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ADC1->SMPR = ADC_SMPR_SMP_2 ;
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/*
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12.5 + 8.5 = 21 ADC Cycles pre ADC sampling
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4 MHz / 21 cycle / 256 = 744 Hz
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*/
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adc_multi_conversion_state++;
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/* fall through */
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case 5:
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if ( adcStartSubTask(ADC_SUB_TASK_ENABLE_ADC) == 0 )
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{
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adcExecSub();
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break;
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}
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adc_multi_conversion_state++;
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/* fall through */
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case 6:
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if ( adcIsSubDone() == 0 )
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{
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adcExecSub();
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break;
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}
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ADC1->CHSELR = 1<<adc_multi_conversion_channel; /* Select channel (can be done also if ADC is enabled) */
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/* conversion will be started automatically with rising edge of TIM2, yet ADSTART is still required */
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ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversion */
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adc_multi_conversion_state++;
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/* fall through */
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case 7:
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if ( DMA1_Channel1->CNDTR > 0 )
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break;
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adc_multi_conversion_state = 0;
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break;
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}
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}
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void scanADC(uint8_t ch, uint16_t cnt, uint8_t *buf)
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{
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stopADC();
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disableADC();
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RCC->AHBENR |= RCC_AHBENR_DMAEN; /* enable DMA clock */
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__NOP(); __NOP(); /* extra delay for clock stabilization required? */
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while( adcStartMultiConversion(ch, cnt, buf) == 0)
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adcExecMultiConversion();
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while( adc_multi_conversion_state != 0 )
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adcExecMultiConversion();
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}
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void __scanADC(uint8_t ch, uint16_t cnt, uint8_t *buf)
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{
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while( adcStartSubTask(ADC_SUB_TASK_STOP_ADC) == 0 )
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adcExecSub();
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while( adcIsSubDone() == 0 )
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adcExecSub();
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while( adcStartSubTask(ADC_SUB_TASK_DISABLE_ADC) == 0 )
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adcExecSub();
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while( adcIsSubDone() == 0 )
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adcExecSub();
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/* disable and reset to defaults */
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DMA1_Channel1->CCR = 0;
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@ -664,7 +768,6 @@ void scanADC(uint8_t ch, uint16_t cnt, uint8_t *buf)
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DMA1_Channel1->CCR |= DMA_CCR_MINC; /* increment memory */
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DMA1_Channel1->CCR |= DMA_CCR_EN; /* enable */
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/*
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detect rising edge on external trigger (ADC_CFGR1_EXTEN_0)
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@ -674,12 +777,12 @@ void scanADC(uint8_t ch, uint16_t cnt, uint8_t *buf)
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Use DMA one shot mode and enable DMA (ADC_CFGR1_DMAEN)
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Once DMA is finished, it will disable continues mode (ADC_CFGR1_CONT)
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*/
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ADC1->CFGR1 =
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ADC_CFGR1_CONT /* continues mode */
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| ADC_CFGR1_EXTEN_0 /* rising edge */
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| ADC_CFGR1_EXTSEL_1 /* TIM2 */
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| ADC_CFGR1_EXTEN_0 /* rising edge */
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// | ADC_CFGR1_EXTEN_1 /* */
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| ADC_CFGR1_EXTSEL_1 /* EXTSEL 010: TIM2 */
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// | ADC_CFGR1_RES_1 /* 8 Bit resolution, no value means 12 bit */
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| ADC_CFGR1_DMAEN; /* enable generation of DMA requests */
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@ -693,12 +796,18 @@ void scanADC(uint8_t ch, uint16_t cnt, uint8_t *buf)
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4 MHz / 21 cycle / 256 = 744 Hz
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*/
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enableADC();
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while( adcStartSubTask(ADC_SUB_TASK_ENABLE_ADC) == 0 )
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adcExecSub();
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while( adcIsSubDone() == 0 )
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adcExecSub();
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ADC1->CHSELR = 1<<ch; /* Select channel (can be done also if ADC is enabled) */
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/* conversion will be started automatically with rising edge of TIM2, yet ADSTART is still required */
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/* conversion will be started automatically with rising edge of TIM2 */
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/* setting ADSTART is still required, see chap 13.4.10 */
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ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversion */
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ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversion with next event */
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/* wait until DMA is completed */
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while ( DMA1_Channel1->CNDTR > 0 )
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