update
This commit is contained in:
olikraus
parent
d7d38934a6
commit
ab992a7495
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@ -44,8 +44,14 @@ void __attribute__ ((interrupt, used)) RTC_IRQHandler(void)
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/* the wake up time flag must be cleared, otherwise no further IRQ will happen */
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/* in principle, this should happen only when a IRQ line 20 IRQ happens, but */
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/* it will be more safe to clear this flag for any interrupt */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
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PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
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RTC->ISR &= ~RTC_ISR_WUTF; /* clear the wake up flag */
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PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR and RTC */
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RCC->APB1ENR &= ~RCC_APB1ENR_PWREN; /* disable power interface */
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RTCIRQCount++;
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}
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@ -58,7 +64,7 @@ void __attribute__ ((interrupt, used)) RTC_IRQHandler(void)
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This must be executed after each reset.
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*/
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void setHSIClock()
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void startHSIClock()
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{
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/* test if the current clock source is something else than HSI */
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if ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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@ -145,10 +151,97 @@ void initDisplay(void)
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u8g2_SendBuffer(&u8g2);
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}
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/*=======================================================================*/
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/*
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configure and start RTC
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This must be executed only after POR reset.
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*/
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void initRTC(void)
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{
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/* real time clock enable */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
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PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
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RTC->WPR = 0x0ca; /* disable RTC write protection */
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RTC->WPR = 0x053;
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/* externel 32K clock source */
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RCC->CSR |= RCC_CSR_LSEBYP; /* bypass oscillator */
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/* externel 32K oscillator */
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//RCC->CSR &= ~RCC_CSR_LSEBYP; /* no bypass oscillator */
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//RCC->CSR &= ~RCC_CSR_LSEDRV_Msk /* lowest drive */
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//RCC->CSR |= RCC_CSR_LSEDRV_0; /* medium low drive */
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RCC->CSR |= RCC_CSR_LSEON; /* enable low speed external clock */
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delay_micro_seconds(100000*5); /* LSE requires between 100ms to 200ms */
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/*
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if ( RCC->CSR & RCC_CSR_LSERDY )
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display_Write("32K Clock Ready\n");
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else
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display_Write("32K Clock Error\n");
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*/
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RCC->CSR &= ~RCC_CSR_RTCSEL_Msk; /* no clock selection for RTC */
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RCC->CSR |= RCC_CSR_RTCSEL_LSE; /* select LSE */
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RCC->CSR |= RCC_CSR_RTCEN; /* enable RTC */
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/* RTC Start */
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RTC->ISR = RTC_ISR_INIT; /* request RTC stop */
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while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF) /* wait for stop */
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;
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RTC->PRER = 0x07f00ff;
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RTC->TR = 0;
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RTC->ISR =~ RTC_ISR_INIT; /* start RTC */
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RTC->WPR = 0; /* enable RTC write protection */
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RTC->WPR = 0;
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PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR and RTC */
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RCC->APB1ENR &= ~RCC_APB1ENR_PWREN; /* disable power interface */
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}
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/*=======================================================================*/
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/*
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enable RTC wakeup and interrupt
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This must be executed after any reset.
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*/
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void startRTCWakeUp(void)
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{
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/* wake up time setup & start */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
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PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
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RTC->WPR = 0x0ca; /* disable RTC write protection */
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RTC->WPR = 0x053;
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RTC->CR &=~ RTC_CR_WUTE; /* disable wakeup timer for reprogramming */
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while((RTC->ISR & RTC_ISR_WUTWF) != RTC_ISR_WUTWF)
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;
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RTC->WUTR = 0; /* reload is 1: 1Hz with the 1Hz clock */
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RTC->CR &= ~RTC_CR_WUCKSEL; /* clear selection register */
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RTC->CR |= RTC_CR_WUCKSEL_2; /* select the 1Hz clock */
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RTC->CR |= RTC_CR_WUTE | RTC_CR_WUTIE ;
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RTC->ISR &= ~RTC_ISR_WUTF; /* clear the wake up flag... is this required? */
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/* wake up IRQ is connected to line 20 */
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EXTI->RTSR |= EXTI_RTSR_RT20; /* rising edge for wake up line */
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EXTI->IMR |= EXTI_IMR_IM20; /* interrupt enable */
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RTC->WPR = 0; /* enable RTC write protection */
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RTC->WPR = 0;
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PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR and RTC */
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RCC->APB1ENR &= ~RCC_APB1ENR_PWREN; /* disable power interface */
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}
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/*=======================================================================*/
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int main()
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{
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setHSIClock();
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startHSIClock();
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SystemCoreClockUpdate(); /* Update SystemCoreClock() */
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//SystemCoreClock = 32000000UL;
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startSysTick();
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@ -178,76 +271,13 @@ int main()
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initDisplay();
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initRTC();
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startRTCWakeUp();
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/* real time clock enable */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
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PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
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/* externel 32K clock source */
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RCC->CSR |= RCC_CSR_LSEBYP; /* bypass oscillator */
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/* externel 32K oscillator */
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//RCC->CSR &= ~RCC_CSR_LSEBYP; /* no bypass oscillator */
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//RCC->CSR &= ~RCC_CSR_LSEDRV_Msk /* lowest drive */
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//RCC->CSR |= RCC_CSR_LSEDRV_0; /* medium low drive */
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RCC->CSR |= RCC_CSR_LSEON; /* enable low speed external clock */
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delay_micro_seconds(100000*5); /* LSE requires between 100ms to 200ms */
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/*
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if ( RCC->CSR & RCC_CSR_LSERDY )
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display_Write("32K Clock Ready\n");
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else
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display_Write("32K Clock Error\n");
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*/
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RCC->CSR &= ~RCC_CSR_RTCSEL_Msk; /* no clock selection for RTC */
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RCC->CSR |= RCC_CSR_RTCSEL_LSE; /* select LSE */
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RCC->CSR |= RCC_CSR_RTCEN; /* enable RTC */
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RTC->WPR = 0x0ca; /* disable RTC write protection */
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RTC->WPR = 0x053;
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/* RTC Start */
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RTC->ISR = RTC_ISR_INIT; /* request RTC stop */
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while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF) /* wait for stop */
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;
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RTC->PRER = 0x07f00ff;
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RTC->TR = 0;
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RTC->ISR =~ RTC_ISR_INIT; /* start RTC */
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PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR and RTC */
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RCC->APB1ENR &= ~RCC_APB1ENR_PWREN; /* disable power interface */
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/* wake up time setup & start */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
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PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
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RTC->CR &=~ RTC_CR_WUTE; /* disable wakeup timer for reprogramming */
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while((RTC->ISR & RTC_ISR_WUTWF) != RTC_ISR_WUTWF)
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;
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RTC->WUTR = 0; /* reload is 1: 1Hz with the 1Hz clock */
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RTC->CR &= ~RTC_CR_WUCKSEL; /* clear selection register */
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RTC->CR |= RTC_CR_WUCKSEL_2; /* select the 1Hz clock */
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RTC->CR |= RTC_CR_WUTE | RTC_CR_WUTIE ;
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RTC->ISR &= ~RTC_ISR_WUTF; /* clear the wake up flag... is this required? */
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RTC->WPR = 0; /* enable RTC write protection */
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RTC->WPR = 0;
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/* wake up IRQ is connected to line 20 */
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EXTI->RTSR |= EXTI_RTSR_RT20; /* rising edge for wake up line */
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EXTI->IMR |= EXTI_IMR_IM20; /* interrupt enable */
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NVIC_EnableIRQ(RTC_IRQn);
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NVIC_SetPriority(RTC_IRQn, 0);
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NVIC_EnableIRQ(RTC_IRQn);
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PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR and RTC */
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RCC->APB1ENR &= ~RCC_APB1ENR_PWREN; /* disable power interface */
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for(;;)
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{
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