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work on none clipping mode

This commit is contained in:
olikraus 2017-11-18 13:06:01 +01:00
parent 59a65d7f1a
commit a20f7e3eec
3 changed files with 49 additions and 29 deletions
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15
csrc/u8g2_hvline.c
View File

@ -54,7 +54,7 @@
Description:
clip range from a (included) to b (excluded) agains c (included) to d (excluded)
Assumptions:
a <= b (this is checked and handled correctly)
a <= b (violation is checked and handled correctly)
c <= d (this is not checked)
will return 0 if there is no intersection and if a > b
@ -105,12 +105,14 @@ static uint8_t u8g2_clip_intersection(u8g2_uint_t *ap, u8g2_uint_t *bp, u8g2_uin
/*
x,y Upper left position of the line
x,y Upper left position of the line within the pixel buffer
len length of the line in pixel, len must not be 0
dir 0: horizontal line (left to right)
1: vertical line (top to bottom)
This function first adjusts the y position to the local buffer. Then it
will clip the line and call u8g2_draw_low_level_hv_line()
*/
static void u8g2_draw_hv_line_2dir(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)
@ -118,9 +120,6 @@ static void u8g2_draw_hv_line_2dir(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u
u8g2_uint_t a;
register u8g2_uint_t w, h;
y -= u8g2->tile_curr_row*8;
h = u8g2->pixel_buf_height; // this must be the real buffer height
w = u8g2->pixel_buf_width; // this could be replaced by u8g2->u8x8.display_info->pixel_width
@ -155,7 +154,7 @@ static void u8g2_draw_hv_line_2dir(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u
#endif
/*
x,y Upper left position of the line
x,y Upper left position of the line (full screen coordinates)
len length of the line in pixel, len must not be 0
dir 0: horizontal line (left to right)
1: vertical line (top to bottom)
@ -171,13 +170,15 @@ void u8g2_draw_hv_line_4dir(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uin
u8g2->hv_cnt++;
#endif /* U8G2_WITH_HVLINE_COUNT */
/* transform to pixel buffer coordinates */
y -= u8g2->tile_curr_row*8;
/* additional optimization for one pixel draw */
/* requires about 60 bytes on the ATMega flash memory */
/* 20% improvement for single pixel draw test in FPS.ino */
#ifdef U8G2_WITH_ONE_PIXEL_OPTIMIZATION
if ( len == 1 )
{
y -= u8g2->tile_curr_row*8;
if ( x < u8g2->pixel_buf_width && y < u8g2->pixel_buf_height )
u8g2->ll_hvline(u8g2, x, y, len, dir);
return;

61
sys/arm/stm32l031x6/tim_scope/main.c
View File

@ -199,6 +199,8 @@ void initADC(void)
ADC1->IER = 0; /* do not allow any interrupts */
ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* select HSI16 clock */
ADC1->CFGR1 |= ADC_CFGR1_RES_1; /* 8 bit resolution */
ADC1->CR |= ADC_CR_ADVREGEN; /* enable ADC voltage regulator, probably not required, because this is automatically activated */
ADC->CCR |= ADC_CCR_VREFEN; /* Wake-up the VREFINT */
@ -211,7 +213,7 @@ void initADC(void)
if ((ADC1->CR & ADC_CR_ADEN) != 0) /* clear ADEN flag if required */
{
/* is this correct, i think we must use the disable flag here */
/* is this correct? i think we must use the disable flag here */
ADC1->CR &= (uint32_t)(~ADC_CR_ADEN);
}
ADC1->CR |= ADC_CR_ADCAL; /* start calibration */
@ -226,6 +228,26 @@ void initADC(void)
__NOP();
__NOP();
/* CONFIGURATION with ADEN=0 */
if ((ADC1->CR & ADC_CR_ADEN) != 0) /* clear ADEN flag if required */
{
/* is this correct? i think we must use the disable flag here */
ADC1->CR |= ADC_CR_ADDIS;
while(ADC1->CR & ADC_CR_ADDIS)
;
}
__NOP(); /* not sure why, but some nop's are required here, at least 4 of them */
__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
//ADC1->CFGR1 &= ~ADC_CFGR1_RES; /* 12 bit resolution */
ADC1->CFGR1 |= ADC_CFGR1_RES_1; /* 8 bit resolution */
/* ENABLE ADC */
ADC1->ISR |= ADC_ISR_ADRDY; /* clear ready flag */
@ -257,32 +279,23 @@ void initADC(void)
*/
uint16_t getADC(uint8_t ch)
{
uint32_t data;
uint32_t i;
//uint32_t i;
/* CONFIGURE ADC */
ADC1->CFGR1 &= ~ADC_CFGR1_EXTEN; /* software enabled conversion start */
ADC1->CFGR1 &= ~ADC_CFGR1_ALIGN; /* right alignment */
ADC1->CFGR1 &= ~ADC_CFGR1_RES; /* 12 bit resolution */
//ADC1->CFGR1 &= ~ADC_CFGR1_EXTEN; /* software enabled conversion start */
//ADC1->CFGR1 &= ~ADC_CFGR1_ALIGN; /* right alignment */
ADC1->CHSELR = 1<<ch; /* Select channel */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* Select a sampling mode of 111 (very slow)*/
//ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* Select a sampling mode of 111 (very slow)*/
/* DO CONVERSION */
data = 0;
for( i = 0; i < 8; i++ )
{
ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversion */
while ((ADC1->ISR & ADC_ISR_EOC) == 0) /* wait end of conversion */
{
}
data += ADC1->DR; /* get ADC result and clear the ISR_EOC flag */
}
data >>= 3;
return data;
return ADC1->DR;
}
/*=======================================================================*/
@ -352,6 +365,7 @@ void main()
{
uint16_t adc_value;
uint16_t i;
u8g2_uint_t y, yy;
setHSIClock(); /* enable 32 MHz Clock */
startUp(); /* enable systick irq and several power regions */
@ -377,21 +391,26 @@ void main()
u8g2_ClearBuffer(&u8g2);
setRow(10); outStr("ADC Test");
setRow(20); outStr("ch5 pin11: ");
adc_value = getADC(5);
adc_value = getADC(5)*16;
TIM2->CCR2 = adc_value;
setRow(30); outHex16(adc_value);
setRow(10); outHex16(adc_value);
TIM2->SR &= ~TIM_SR_UIF;
while( (TIM2->SR & TIM_SR_UIF) == 0 )
;
for( i = 0; i < 10; i++ )
yy = 60;
for( i = 0; i < 128; i++ )
{
u8g2_DrawPixel(&u8g2, i, 60);
y = 60-(getADC(6)>>2);
u8g2_DrawPixel(&u8g2, i, y);
if ( y < yy )
u8g2_DrawVLine(&u8g2, i, y, yy-y+1);
else
u8g2_DrawVLine(&u8g2, i, yy, y-yy+1);
yy = y;
}
u8g2_SendBuffer(&u8g2);

2
sys/sdl/text_picture_loop/main.c
View File

@ -16,7 +16,7 @@ int main(void)
u8x8_InitDisplay(u8g2_GetU8x8(&u8g2));
u8x8_SetPowerSave(u8g2_GetU8x8(&u8g2), 0);
u8g2_SetFont(&u8g2, u8g2_font_helvB18_tr);
u8g2_SetFont(&u8g2, u8g2_font_helvB12_tr);
x = 50;
y = 30;