issue #1050 winstar ssd1327 96x64
This commit is contained in:
kraus
parent
26a73c2ca0
commit
761768577a
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@ -234,5 +234,5 @@ https://github.com/olikraus/u8g2 ChangeLog
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* Support for IST7920 (issue 999). Note: IST7920 has nothing todo with ST7920
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* Added screenshot/screencapture for full buffer mode (issue 1005)
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* Bugfix for draw 1x2 and 2x2 procedures for big 8x8 fonts (issue 1054)
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* Added fast software SPI support for Arduino Nano Every (issue 987)
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162
cppsrc/U8g2lib.h
162
cppsrc/U8g2lib.h
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@ -5816,6 +5816,168 @@ class U8G2_SSD1326_ER_256X32_F_2ND_HW_I2C : public U8G2 {
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u8x8_SetPin_HW_I2C(getU8x8(), reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_1_4W_SW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_1_4W_SW_SPI(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_1(&u8g2, rotation, u8x8_byte_arduino_4wire_sw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_4Wire_SW_SPI(getU8x8(), clock, data, cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_1_4W_HW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_1_4W_HW_SPI(const u8g2_cb_t *rotation, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_1(&u8g2, rotation, u8x8_byte_arduino_hw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_4Wire_HW_SPI(getU8x8(), cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_1_2ND_4W_HW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_1_2ND_4W_HW_SPI(const u8g2_cb_t *rotation, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_1(&u8g2, rotation, u8x8_byte_arduino_2nd_hw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_4Wire_HW_SPI(getU8x8(), cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_1_3W_SW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_1_3W_SW_SPI(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t cs, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_1(&u8g2, rotation, u8x8_byte_arduino_3wire_sw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_3Wire_SW_SPI(getU8x8(), clock, data, cs, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_1_6800 : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_1_6800(const u8g2_cb_t *rotation, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_1(&u8g2, rotation, u8x8_byte_8bit_6800mode, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_8Bit_6800(getU8x8(), d0, d1, d2, d3, d4, d5, d6, d7, enable, cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_1_8080 : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_1_8080(const u8g2_cb_t *rotation, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_1(&u8g2, rotation, u8x8_byte_arduino_8bit_8080mode, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_8Bit_8080(getU8x8(), d0, d1, d2, d3, d4, d5, d6, d7, enable, cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_2_4W_SW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_2_4W_SW_SPI(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_2(&u8g2, rotation, u8x8_byte_arduino_4wire_sw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_4Wire_SW_SPI(getU8x8(), clock, data, cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_2_4W_HW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_2_4W_HW_SPI(const u8g2_cb_t *rotation, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_2(&u8g2, rotation, u8x8_byte_arduino_hw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_4Wire_HW_SPI(getU8x8(), cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_2_2ND_4W_HW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_2_2ND_4W_HW_SPI(const u8g2_cb_t *rotation, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_2(&u8g2, rotation, u8x8_byte_arduino_2nd_hw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_4Wire_HW_SPI(getU8x8(), cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_2_3W_SW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_2_3W_SW_SPI(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t cs, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_2(&u8g2, rotation, u8x8_byte_arduino_3wire_sw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_3Wire_SW_SPI(getU8x8(), clock, data, cs, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_2_6800 : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_2_6800(const u8g2_cb_t *rotation, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_2(&u8g2, rotation, u8x8_byte_8bit_6800mode, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_8Bit_6800(getU8x8(), d0, d1, d2, d3, d4, d5, d6, d7, enable, cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_2_8080 : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_2_8080(const u8g2_cb_t *rotation, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_2(&u8g2, rotation, u8x8_byte_arduino_8bit_8080mode, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_8Bit_8080(getU8x8(), d0, d1, d2, d3, d4, d5, d6, d7, enable, cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_F_4W_SW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_F_4W_SW_SPI(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_f(&u8g2, rotation, u8x8_byte_arduino_4wire_sw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_4Wire_SW_SPI(getU8x8(), clock, data, cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_F_4W_HW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_F_4W_HW_SPI(const u8g2_cb_t *rotation, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_f(&u8g2, rotation, u8x8_byte_arduino_hw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_4Wire_HW_SPI(getU8x8(), cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_F_2ND_4W_HW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_F_2ND_4W_HW_SPI(const u8g2_cb_t *rotation, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_f(&u8g2, rotation, u8x8_byte_arduino_2nd_hw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_4Wire_HW_SPI(getU8x8(), cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_F_3W_SW_SPI : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_F_3W_SW_SPI(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t cs, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_f(&u8g2, rotation, u8x8_byte_arduino_3wire_sw_spi, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_3Wire_SW_SPI(getU8x8(), clock, data, cs, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_F_6800 : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_F_6800(const u8g2_cb_t *rotation, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_f(&u8g2, rotation, u8x8_byte_8bit_6800mode, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_8Bit_6800(getU8x8(), d0, d1, d2, d3, d4, d5, d6, d7, enable, cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_F_8080 : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_F_8080(const u8g2_cb_t *rotation, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_ws_96x64_f(&u8g2, rotation, u8x8_byte_arduino_8bit_8080mode, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_8Bit_8080(getU8x8(), d0, d1, d2, d3, d4, d5, d6, d7, enable, cs, dc, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_1_SW_I2C : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_1_SW_I2C(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_i2c_ws_96x64_1(&u8g2, rotation, u8x8_byte_arduino_sw_i2c, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_SW_I2C(getU8x8(), clock, data, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_1_HW_I2C : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_1_HW_I2C(const u8g2_cb_t *rotation, uint8_t reset = U8X8_PIN_NONE, uint8_t clock = U8X8_PIN_NONE, uint8_t data = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_i2c_ws_96x64_1(&u8g2, rotation, u8x8_byte_arduino_hw_i2c, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_HW_I2C(getU8x8(), reset, clock, data);
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}
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};
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class U8G2_SSD1327_WS_96X64_1_2ND_HW_I2C : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_1_2ND_HW_I2C(const u8g2_cb_t *rotation, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_i2c_ws_96x64_1(&u8g2, rotation, u8x8_byte_arduino_2nd_hw_i2c, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_HW_I2C(getU8x8(), reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_2_SW_I2C : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_2_SW_I2C(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_i2c_ws_96x64_2(&u8g2, rotation, u8x8_byte_arduino_sw_i2c, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_SW_I2C(getU8x8(), clock, data, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_2_HW_I2C : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_2_HW_I2C(const u8g2_cb_t *rotation, uint8_t reset = U8X8_PIN_NONE, uint8_t clock = U8X8_PIN_NONE, uint8_t data = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_i2c_ws_96x64_2(&u8g2, rotation, u8x8_byte_arduino_hw_i2c, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_HW_I2C(getU8x8(), reset, clock, data);
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}
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};
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class U8G2_SSD1327_WS_96X64_2_2ND_HW_I2C : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_2_2ND_HW_I2C(const u8g2_cb_t *rotation, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_i2c_ws_96x64_2(&u8g2, rotation, u8x8_byte_arduino_2nd_hw_i2c, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_HW_I2C(getU8x8(), reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_F_SW_I2C : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_F_SW_I2C(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_i2c_ws_96x64_f(&u8g2, rotation, u8x8_byte_arduino_sw_i2c, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_SW_I2C(getU8x8(), clock, data, reset);
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}
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};
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class U8G2_SSD1327_WS_96X64_F_HW_I2C : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_F_HW_I2C(const u8g2_cb_t *rotation, uint8_t reset = U8X8_PIN_NONE, uint8_t clock = U8X8_PIN_NONE, uint8_t data = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_i2c_ws_96x64_f(&u8g2, rotation, u8x8_byte_arduino_hw_i2c, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_HW_I2C(getU8x8(), reset, clock, data);
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}
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};
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class U8G2_SSD1327_WS_96X64_F_2ND_HW_I2C : public U8G2 {
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public: U8G2_SSD1327_WS_96X64_F_2ND_HW_I2C(const u8g2_cb_t *rotation, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_i2c_ws_96x64_f(&u8g2, rotation, u8x8_byte_arduino_2nd_hw_i2c, u8x8_gpio_and_delay_arduino);
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u8x8_SetPin_HW_I2C(getU8x8(), reset);
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}
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};
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class U8G2_SSD1327_SEEED_96X96_1_4W_SW_SPI : public U8G2 {
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public: U8G2_SSD1327_SEEED_96X96_1_4W_SW_SPI(const u8g2_cb_t *rotation, uint8_t clock, uint8_t data, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8G2() {
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u8g2_Setup_ssd1327_seeed_96x96_1(&u8g2, rotation, u8x8_byte_arduino_4wire_sw_spi, u8x8_gpio_and_delay_arduino);
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@ -2191,6 +2191,60 @@ class U8X8_SSD1326_ER_256X32_2ND_HW_I2C : public U8X8 {
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u8x8_SetPin_HW_I2C(getU8x8(), reset);
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}
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};
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class U8X8_SSD1327_WS_96X64_4W_SW_SPI : public U8X8 {
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public: U8X8_SSD1327_WS_96X64_4W_SW_SPI(uint8_t clock, uint8_t data, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8X8() {
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u8x8_Setup(getU8x8(), u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, u8x8_byte_arduino_4wire_sw_spi, u8x8_gpio_and_delay_arduino);
|
||||
u8x8_SetPin_4Wire_SW_SPI(getU8x8(), clock, data, cs, dc, reset);
|
||||
}
|
||||
};
|
||||
class U8X8_SSD1327_WS_96X64_4W_HW_SPI : public U8X8 {
|
||||
public: U8X8_SSD1327_WS_96X64_4W_HW_SPI(uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8X8() {
|
||||
u8x8_Setup(getU8x8(), u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, u8x8_byte_arduino_hw_spi, u8x8_gpio_and_delay_arduino);
|
||||
u8x8_SetPin_4Wire_HW_SPI(getU8x8(), cs, dc, reset);
|
||||
}
|
||||
};
|
||||
class U8X8_SSD1327_WS_96X64_2ND_4W_HW_SPI : public U8X8 {
|
||||
public: U8X8_SSD1327_WS_96X64_2ND_4W_HW_SPI(uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8X8() {
|
||||
u8x8_Setup(getU8x8(), u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, u8x8_byte_arduino_2nd_hw_spi, u8x8_gpio_and_delay_arduino);
|
||||
u8x8_SetPin_4Wire_HW_SPI(getU8x8(), cs, dc, reset);
|
||||
}
|
||||
};
|
||||
class U8X8_SSD1327_WS_96X64_3W_SW_SPI : public U8X8 {
|
||||
public: U8X8_SSD1327_WS_96X64_3W_SW_SPI(uint8_t clock, uint8_t data, uint8_t cs, uint8_t reset = U8X8_PIN_NONE) : U8X8() {
|
||||
u8x8_Setup(getU8x8(), u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, u8x8_byte_arduino_3wire_sw_spi, u8x8_gpio_and_delay_arduino);
|
||||
u8x8_SetPin_3Wire_SW_SPI(getU8x8(), clock, data, cs, reset);
|
||||
}
|
||||
};
|
||||
class U8X8_SSD1327_WS_96X64_6800 : public U8X8 {
|
||||
public: U8X8_SSD1327_WS_96X64_6800(uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8X8() {
|
||||
u8x8_Setup(getU8x8(), u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, u8x8_byte_8bit_6800mode, u8x8_gpio_and_delay_arduino);
|
||||
u8x8_SetPin_8Bit_6800(getU8x8(), d0, d1, d2, d3, d4, d5, d6, d7, enable, cs, dc, reset);
|
||||
}
|
||||
};
|
||||
class U8X8_SSD1327_WS_96X64_8080 : public U8X8 {
|
||||
public: U8X8_SSD1327_WS_96X64_8080(uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8X8() {
|
||||
u8x8_Setup(getU8x8(), u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, u8x8_byte_arduino_8bit_8080mode, u8x8_gpio_and_delay_arduino);
|
||||
u8x8_SetPin_8Bit_8080(getU8x8(), d0, d1, d2, d3, d4, d5, d6, d7, enable, cs, dc, reset);
|
||||
}
|
||||
};
|
||||
class U8X8_SSD1327_WS_96X64_SW_I2C : public U8X8 {
|
||||
public: U8X8_SSD1327_WS_96X64_SW_I2C(uint8_t clock, uint8_t data, uint8_t reset = U8X8_PIN_NONE) : U8X8() {
|
||||
u8x8_Setup(getU8x8(), u8x8_d_ssd1327_ws_96x64, u8x8_cad_ssd13xx_i2c, u8x8_byte_arduino_sw_i2c, u8x8_gpio_and_delay_arduino);
|
||||
u8x8_SetPin_SW_I2C(getU8x8(), clock, data, reset);
|
||||
}
|
||||
};
|
||||
class U8X8_SSD1327_WS_96X64_HW_I2C : public U8X8 {
|
||||
public: U8X8_SSD1327_WS_96X64_HW_I2C(uint8_t reset = U8X8_PIN_NONE, uint8_t clock = U8X8_PIN_NONE, uint8_t data = U8X8_PIN_NONE) : U8X8() {
|
||||
u8x8_Setup(getU8x8(), u8x8_d_ssd1327_ws_96x64, u8x8_cad_ssd13xx_i2c, u8x8_byte_arduino_hw_i2c, u8x8_gpio_and_delay_arduino);
|
||||
u8x8_SetPin_HW_I2C(getU8x8(), reset, clock, data);
|
||||
}
|
||||
};
|
||||
class U8X8_SSD1327_WS_96X64_2ND_HW_I2C : public U8X8 {
|
||||
public: U8X8_SSD1327_WS_96X64_2ND_HW_I2C(uint8_t reset = U8X8_PIN_NONE) : U8X8() {
|
||||
u8x8_Setup(getU8x8(), u8x8_d_ssd1327_ws_96x64, u8x8_cad_ssd13xx_i2c, u8x8_byte_arduino_2nd_hw_i2c, u8x8_gpio_and_delay_arduino);
|
||||
u8x8_SetPin_HW_I2C(getU8x8(), reset);
|
||||
}
|
||||
};
|
||||
class U8X8_SSD1327_SEEED_96X96_4W_SW_SPI : public U8X8 {
|
||||
public: U8X8_SSD1327_SEEED_96X96_4W_SW_SPI(uint8_t clock, uint8_t data, uint8_t cs, uint8_t dc, uint8_t reset = U8X8_PIN_NONE) : U8X8() {
|
||||
u8x8_Setup(getU8x8(), u8x8_d_ssd1327_seeed_96x96, u8x8_cad_001, u8x8_byte_arduino_4wire_sw_spi, u8x8_gpio_and_delay_arduino);
|
||||
|
|
|
|||
|
|
@ -471,6 +471,9 @@ uint8_t *u8g2_m_16_12_f(uint8_t *page_cnt);
|
|||
uint8_t *u8g2_m_32_4_1(uint8_t *page_cnt);
|
||||
uint8_t *u8g2_m_32_4_2(uint8_t *page_cnt);
|
||||
uint8_t *u8g2_m_32_4_f(uint8_t *page_cnt);
|
||||
uint8_t *u8g2_m_12_8_1(uint8_t *page_cnt);
|
||||
uint8_t *u8g2_m_12_8_2(uint8_t *page_cnt);
|
||||
uint8_t *u8g2_m_12_8_f(uint8_t *page_cnt);
|
||||
uint8_t *u8g2_m_24_4_1(uint8_t *page_cnt);
|
||||
uint8_t *u8g2_m_24_4_2(uint8_t *page_cnt);
|
||||
uint8_t *u8g2_m_24_4_f(uint8_t *page_cnt);
|
||||
|
|
@ -767,6 +770,12 @@ void u8g2_Setup_ssd1326_er_256x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x
|
|||
void u8g2_Setup_ssd1326_i2c_er_256x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1326_i2c_er_256x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1326_i2c_er_256x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1327_ws_96x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1327_ws_96x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1327_ws_96x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1327_i2c_ws_96x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1327_i2c_ws_96x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1327_i2c_ws_96x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1327_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1327_seeed_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
void u8g2_Setup_ssd1327_seeed_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);
|
||||
|
|
|
|||
|
|
@ -465,6 +465,39 @@ uint8_t *u8g2_m_32_4_f(uint8_t *page_cnt)
|
|||
return buf;
|
||||
#endif
|
||||
}
|
||||
uint8_t *u8g2_m_12_8_1(uint8_t *page_cnt)
|
||||
{
|
||||
#ifdef U8G2_USE_DYNAMIC_ALLOC
|
||||
*page_cnt = 1;
|
||||
return 0;
|
||||
#else
|
||||
static uint8_t buf[96];
|
||||
*page_cnt = 1;
|
||||
return buf;
|
||||
#endif
|
||||
}
|
||||
uint8_t *u8g2_m_12_8_2(uint8_t *page_cnt)
|
||||
{
|
||||
#ifdef U8G2_USE_DYNAMIC_ALLOC
|
||||
*page_cnt = 2;
|
||||
return 0;
|
||||
#else
|
||||
static uint8_t buf[192];
|
||||
*page_cnt = 2;
|
||||
return buf;
|
||||
#endif
|
||||
}
|
||||
uint8_t *u8g2_m_12_8_f(uint8_t *page_cnt)
|
||||
{
|
||||
#ifdef U8G2_USE_DYNAMIC_ALLOC
|
||||
*page_cnt = 8;
|
||||
return 0;
|
||||
#else
|
||||
static uint8_t buf[768];
|
||||
*page_cnt = 8;
|
||||
return buf;
|
||||
#endif
|
||||
}
|
||||
uint8_t *u8g2_m_24_4_1(uint8_t *page_cnt)
|
||||
{
|
||||
#ifdef U8G2_USE_DYNAMIC_ALLOC
|
||||
|
|
|
|||
|
|
@ -1829,6 +1829,62 @@ void u8g2_Setup_ssd1326_i2c_er_256x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation,
|
|||
}
|
||||
/* ssd1327 */
|
||||
/* ssd1327 1 */
|
||||
void u8g2_Setup_ssd1327_ws_96x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)
|
||||
{
|
||||
uint8_t tile_buf_height;
|
||||
uint8_t *buf;
|
||||
u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);
|
||||
buf = u8g2_m_12_8_1(&tile_buf_height);
|
||||
u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);
|
||||
}
|
||||
/* ssd1327 2 */
|
||||
void u8g2_Setup_ssd1327_ws_96x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)
|
||||
{
|
||||
uint8_t tile_buf_height;
|
||||
uint8_t *buf;
|
||||
u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);
|
||||
buf = u8g2_m_12_8_2(&tile_buf_height);
|
||||
u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);
|
||||
}
|
||||
/* ssd1327 f */
|
||||
void u8g2_Setup_ssd1327_ws_96x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)
|
||||
{
|
||||
uint8_t tile_buf_height;
|
||||
uint8_t *buf;
|
||||
u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);
|
||||
buf = u8g2_m_12_8_f(&tile_buf_height);
|
||||
u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);
|
||||
}
|
||||
/* ssd1327 */
|
||||
/* ssd1327 1 */
|
||||
void u8g2_Setup_ssd1327_i2c_ws_96x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)
|
||||
{
|
||||
uint8_t tile_buf_height;
|
||||
uint8_t *buf;
|
||||
u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);
|
||||
buf = u8g2_m_12_8_1(&tile_buf_height);
|
||||
u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);
|
||||
}
|
||||
/* ssd1327 2 */
|
||||
void u8g2_Setup_ssd1327_i2c_ws_96x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)
|
||||
{
|
||||
uint8_t tile_buf_height;
|
||||
uint8_t *buf;
|
||||
u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);
|
||||
buf = u8g2_m_12_8_2(&tile_buf_height);
|
||||
u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);
|
||||
}
|
||||
/* ssd1327 f */
|
||||
void u8g2_Setup_ssd1327_i2c_ws_96x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)
|
||||
{
|
||||
uint8_t tile_buf_height;
|
||||
uint8_t *buf;
|
||||
u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);
|
||||
buf = u8g2_m_12_8_f(&tile_buf_height);
|
||||
u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);
|
||||
}
|
||||
/* ssd1327 */
|
||||
/* ssd1327 1 */
|
||||
void u8g2_Setup_ssd1327_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)
|
||||
{
|
||||
uint8_t tile_buf_height;
|
||||
|
|
|
|||
|
|
@ -886,6 +886,7 @@ uint8_t u8x8_d_ra8835_nhd_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, vo
|
|||
uint8_t u8x8_d_ra8835_320x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
|
||||
uint8_t u8x8_d_ssd1325_nhd_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
|
||||
uint8_t u8x8_d_ssd0323_os128064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
|
||||
uint8_t u8x8_d_ssd1327_ws_96x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
|
||||
uint8_t u8x8_d_ssd1327_seeed_96x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
|
||||
uint8_t u8x8_d_ssd1327_ea_w128128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
|
||||
uint8_t u8x8_d_ssd1327_midas_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
|
||||
|
|
|
|||
|
|
@ -52,7 +52,38 @@ static const uint8_t u8x8_d_ssd1327_96x96_powersave1_seq[] = {
|
|||
};
|
||||
|
||||
|
||||
static const uint8_t u8x8_d_ssd1327_seeed_96x96_flip0_seq[] = {
|
||||
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
|
||||
U8X8_CA(0x0a2, 0x020), /* display offset, shift mapping ram counter */
|
||||
U8X8_CA(0x0a0, 0x051), /* remap configuration */
|
||||
U8X8_END_TRANSFER(), /* disable chip */
|
||||
U8X8_END() /* end of sequence */
|
||||
};
|
||||
|
||||
static const uint8_t u8x8_d_ssd1327_seeed_96x96_flip1_seq[] = {
|
||||
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
|
||||
U8X8_CA(0x0a2, 0x060), /* display offset, shift mapping ram counter */
|
||||
U8X8_CA(0x0a0, 0x042), /* remap configuration */
|
||||
U8X8_END_TRANSFER(), /* disable chip */
|
||||
U8X8_END() /* end of sequence */
|
||||
};
|
||||
|
||||
|
||||
static const uint8_t u8x8_d_ssd1327_winstar_96x64_flip0_seq[] = {
|
||||
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
|
||||
U8X8_CA(0x0a0, 0x042), /* remap configuration */
|
||||
U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
|
||||
U8X8_END_TRANSFER(), /* disable chip */
|
||||
U8X8_END() /* end of sequence */
|
||||
};
|
||||
|
||||
static const uint8_t u8x8_d_ssd1327_winstar_96x64_flip1_seq[] = {
|
||||
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
|
||||
U8X8_CA(0x0a0, 0x051), /* remap configuration */
|
||||
U8X8_CA(0x0a2, 0x040), /* display offset, shift mapping ram counter */
|
||||
U8X8_END_TRANSFER(), /* disable chip */
|
||||
U8X8_END() /* end of sequence */
|
||||
};
|
||||
|
||||
/*
|
||||
input:
|
||||
|
|
@ -171,6 +202,139 @@ static uint8_t u8x8_d_ssd1327_96x96_generic(u8x8_t *u8x8, uint8_t msg, uint8_t a
|
|||
return 1;
|
||||
}
|
||||
|
||||
/*=============================================*/
|
||||
/*
|
||||
Winstar WEA009664B 96x64 OLED Display, 1.1 inch OLED
|
||||
https://www.winstar.com.tw/products/oled-module/graphic-oled-display/96x64-oled.html
|
||||
|
||||
https://github.com/olikraus/u8g2/issues/1050
|
||||
*/
|
||||
|
||||
static const u8x8_display_info_t u8x8_ssd1327_winstar_96x64_display_info =
|
||||
{
|
||||
/* chip_enable_level = */ 0,
|
||||
/* chip_disable_level = */ 1,
|
||||
|
||||
/* post_chip_enable_wait_ns = */ 20,
|
||||
/* pre_chip_disable_wait_ns = */ 10,
|
||||
/* reset_pulse_width_ms = */ 100,
|
||||
/* post_reset_wait_ms = */ 100, /**/
|
||||
/* sda_setup_time_ns = */ 100, /* */
|
||||
/* sck_pulse_width_ns = */ 100, /* */
|
||||
/* sck_clock_hz = */ 4000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns */
|
||||
/* spi_mode = */ 0, /* active high, rising edge */
|
||||
/* i2c_bus_clock_100kHz = */ 1, /* use 1 instead of 4, because the SSD1327 seems to be very slow */
|
||||
/* data_setup_time_ns = */ 40,
|
||||
/* write_pulse_width_ns = */ 60,
|
||||
/* tile_width = */ 12,
|
||||
/* tile_hight = */ 8,
|
||||
/* default_x_offset = */ 0,
|
||||
/* flipmode_x_offset = */ 0,
|
||||
/* pixel_width = */ 96,
|
||||
/* pixel_height = */ 64
|
||||
};
|
||||
|
||||
/*
|
||||
Write_Cmd(0xAE); //Set Display Off OK
|
||||
Write_Cmd(0x81); //Contrast Level OK
|
||||
Write_Cmd(0xdF); // VALUE WRONG????
|
||||
Write_Cmd(0xD9); //Pre-charge Period
|
||||
Write_Cmd(0x00);
|
||||
Write_Cmd(0xA0); //Set Re-map OK
|
||||
Write_Cmd(0x42); //Default Setting OK
|
||||
Write_Cmd(0xA1); //Set Display Start Line OK
|
||||
Write_Cmd(0x00); OK
|
||||
Write_Cmd(0xA2); //Set Display Offset OK
|
||||
Write_Cmd(0x00); OK
|
||||
Write_Cmd(0xA4); //Set Display Mode OK
|
||||
Write_Cmd(0xA8); //Set Multiplex Ratio OK
|
||||
Write_Cmd(0x63); //Multiplex OK
|
||||
Write_Cmd(0xAB); //Set Function SelectionA OK
|
||||
Write_Cmd(0x01); OK
|
||||
Write_Cmd(0xB1); //Set Phase Length OK
|
||||
Write_Cmd(0x47); OK
|
||||
Write_Cmd(0xB3); //Set Display Clock Divide Ratio/Oscillator Frequency OK
|
||||
Write_Cmd(0x00); OK
|
||||
Write_Cmd(0xBC); //Set Prechange Voltage OK
|
||||
Write_Cmd(0x07); OK
|
||||
Write_Cmd(0xBE); //Set VCOMH Voltage OK
|
||||
Write_Cmd(0x07); OK
|
||||
Write_Cmd(0xB6); //Set Second Pre-charge period OK
|
||||
Write_Cmd(0x04); OK
|
||||
Write_Cmd(0xD5); //Set Function selection B OK
|
||||
Write_Cmd(0x62); OK
|
||||
Write_Cmd(0xAF); //Set Display On
|
||||
|
||||
*/
|
||||
|
||||
static const uint8_t u8x8_d_ssd1327_winstar_96x64_init_seq[] = {
|
||||
|
||||
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
|
||||
|
||||
U8X8_CA(0x0fd, 0x012), /* unlock display, usually not required because the display is unlocked after reset */
|
||||
U8X8_C(0x0ae), /* display off */
|
||||
|
||||
U8X8_CA(0x0d9, 0x000), /* Pre-charge Period ??? */
|
||||
|
||||
U8X8_CA(0x0a0, 0x042), /* remap configuration */
|
||||
U8X8_CA(0x0a1, 0x000), /* display start line */
|
||||
U8X8_CA(0x0a2, 0x000), /* display offset, shift mapping ram counter */
|
||||
|
||||
U8X8_CA(0x0a8, 63), /* multiplex ratio: 63* 1/64 duty */
|
||||
|
||||
U8X8_CA(0x0ab, 0x001), /* Enable internal VDD regulator (RESET) */
|
||||
U8X8_CA(0x081, 0x053), /* contrast, brightness, 0..128 */
|
||||
|
||||
U8X8_CA(0x0b1, 0x047), /* phase length */
|
||||
//U8X8_CA(0x0b3, 0x001), /* set display clock divide ratio/oscillator frequency */
|
||||
U8X8_CA(0x0b3, 0x000), /* set display clock divide ratio/oscillator frequency */
|
||||
|
||||
U8X8_C(0x0b9), /* use linear lookup table */
|
||||
|
||||
U8X8_CA(0x0bc, 0x007), /* pre-charge voltage level */
|
||||
U8X8_CA(0x0be, 0x007), /* VCOMH voltage */
|
||||
U8X8_CA(0x0b6, 0x004), /* second precharge */
|
||||
U8X8_CA(0x0d5, 0x062), /* enable second precharge, internal vsl (bit0 = 0) */
|
||||
|
||||
U8X8_C(0x0a4), /* normal display mode */
|
||||
|
||||
U8X8_END_TRANSFER(), /* disable chip */
|
||||
U8X8_END() /* end of sequence */
|
||||
};
|
||||
|
||||
uint8_t u8x8_d_ssd1327_ws_96x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
|
||||
{
|
||||
if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )
|
||||
return 1;
|
||||
if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
|
||||
{
|
||||
u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_winstar_96x64_display_info);
|
||||
return 1;
|
||||
}
|
||||
else if ( msg == U8X8_MSG_DISPLAY_INIT )
|
||||
{
|
||||
u8x8_d_helper_display_init(u8x8);
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_winstar_96x64_init_seq);
|
||||
return 1;
|
||||
}
|
||||
else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
|
||||
{
|
||||
if ( arg_int == 0 )
|
||||
{
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_winstar_96x64_flip0_seq);
|
||||
u8x8->x_offset = u8x8->display_info->default_x_offset;
|
||||
}
|
||||
else
|
||||
{
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_winstar_96x64_flip1_seq);
|
||||
u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*=============================================*/
|
||||
/* Seeedstudio Grove OLED 96x96 */
|
||||
|
||||
|
|
@ -259,21 +423,6 @@ static const uint8_t u8x8_d_ssd1327_96x96_init_seq[] = {
|
|||
};
|
||||
|
||||
|
||||
static const uint8_t u8x8_d_ssd1327_seeed_96x96_flip0_seq[] = {
|
||||
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
|
||||
U8X8_CA(0x0a2, 0x020), /* display offset, shift mapping ram counter */
|
||||
U8X8_CA(0x0a0, 0x051), /* remap configuration */
|
||||
U8X8_END_TRANSFER(), /* disable chip */
|
||||
U8X8_END() /* end of sequence */
|
||||
};
|
||||
|
||||
static const uint8_t u8x8_d_ssd1327_seeed_96x96_flip1_seq[] = {
|
||||
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
|
||||
U8X8_CA(0x0a2, 0x060), /* display offset, shift mapping ram counter */
|
||||
U8X8_CA(0x0a0, 0x042), /* remap configuration */
|
||||
U8X8_END_TRANSFER(), /* disable chip */
|
||||
U8X8_END() /* end of sequence */
|
||||
};
|
||||
|
||||
|
||||
uint8_t u8x8_d_ssd1327_seeed_96x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
|
||||
|
|
|
|||
|
|
@ -517,6 +517,23 @@ struct controller controller_list[] =
|
|||
},
|
||||
|
||||
|
||||
{
|
||||
"ssd1327", 12, 8, "u8g2_ll_hvline_vertical_top_lsb", "u8x8_cad_001", "", COM_4WSPI|COM_3WSPI|COM_6800|COM_8080,
|
||||
"", /* is_generate_u8g2_class= */ 1,
|
||||
{
|
||||
{ "ws_96x64" },
|
||||
{ NULL }
|
||||
}
|
||||
},
|
||||
{
|
||||
"ssd1327", 12, 8, "u8g2_ll_hvline_vertical_top_lsb", "u8x8_cad_ssd13xx_i2c", "i2c", COM_I2C,
|
||||
"", /* is_generate_u8g2_class= */ 1,
|
||||
{
|
||||
{ "ws_96x64" },
|
||||
{ NULL }
|
||||
}
|
||||
},
|
||||
|
||||
{
|
||||
"ssd1327", 12, 12, "u8g2_ll_hvline_vertical_top_lsb", "u8x8_cad_001", "", COM_4WSPI|COM_3WSPI|COM_6800|COM_8080,
|
||||
"", /* is_generate_u8g2_class= */ 1,
|
||||
|
|
|
|||
Loading…
Reference in New Issue