2.33.2
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@ -926,6 +926,7 @@ uint8_t u8x8_d_ssd1318_128x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *
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uint8_t u8x8_d_ssd1318_128x96_xcp(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
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uint8_t u8x8_d_ssd1320_160x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
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uint8_t u8x8_d_ssd1320_160x132(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
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uint8_t u8x8_d_ssd1320_160x80(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
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uint8_t u8x8_d_ssd1322_nhd_256x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
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uint8_t u8x8_d_ssd1322_nhd_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
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uint8_t u8x8_d_a2printer_384x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
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@ -40,7 +40,7 @@
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Adapted from u8x8_d_ssd1322.c with the command set of the SSD1320 controller
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"official" procedure is described here: https://github.com/olikraus/u8g2/wiki/internal
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NOTE: U8x8 does NOT work!
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NOTE: U8x8 does NOT work! --> not clear, needs to be checked
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https://github.com/olikraus/u8g2/issues/1816
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@ -608,13 +608,13 @@ uint8_t u8x8_d_ssd1320_160x132(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void
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/*=========================================================*/
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/* https://github.com/olikraus/u8g2/issues/1816 */
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/* 160x80 */
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/* 160x80, https://de.aliexpress.com/item/1005003510267760.html */
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static const uint8_t u8x8_d_ssd1320_160x80_flip0_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0x0a0), /* remap */
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U8X8_C(0xc8), /* Set COM Output Scan Direction: normal mode CS1 */
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U8X8_CA(0xd3, 0x0e), /* CS1 */
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U8X8_CA(0xd3, 39), /* display offset */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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@ -623,7 +623,7 @@ static const uint8_t u8x8_d_ssd1320_160x80_flip1_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0x0a1), /* remap */
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U8X8_C(0xc0), /* Set COM Output Scan Direction: normal mode CS1 */
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U8X8_CA(0xd3, 0x92), /* CS1 */
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U8X8_CA(0xd3, 120), /* display offset */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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@ -660,36 +660,24 @@ static const uint8_t u8x8_d_ssd1320_160x80_init_seq[] = {
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U8X8_DLY(1),
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U8X8_C(0xae), /* display off */
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U8X8_CA(0xd5, 0xC2), /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
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U8X8_CA(0xa8, 0x83), /* multiplex ratio 1/132 Duty */
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U8X8_CA(0xa2, 0x00), /* display start line */
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U8X8_CA(0xa8, 80), /* multiplex ratio 1/80 Duty */
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U8X8_CA(0xa2, 0), /* display start line */
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U8X8_C(0xa0), /* Set Segment Re-Map: column address 0 mapped to SEG0 CS1 */
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// U8X8_C(0xa1), /* Set Segment Re-Map: column address 0 mapped to SEG0 CS2 */
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U8X8_C(0xc8), /* Set COM Output Scan Direction: normal mode CS1 */
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// U8X8_C(0xc0), /* Set COM Output Scan Direction: normal mode CS2 */
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U8X8_C(0xa0), /* Set Segment Re-Map */
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U8X8_C(0xc8), /* Set COM Output Scan Direction: normal mode */
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U8X8_CA(0xad, 0x10), /* select Iref: 0x00 external (reset default), 0x10 internal */
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U8X8_CA(0xbc, 0x1e), /* pre-charge voltage level 0x00..0x1f, reset default: 0x1e */
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U8X8_C(0xbf), /* select linear LUT */
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U8X8_CA(0xd5, 0xc2), /* Bit 0..3: clock ratio 1, 2, 4, 8, ...256, reset=0x1, Bit 4..7: F_osc 0..15 */
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U8X8_CA(0xd9, 0x72), /* Set Phase 1&2 Length, Bit 0..3: Phase 1, Bit 4..7: Phase 2, reset default 0x72 */
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U8X8_CA(0xbd, 0x03), /* from the vendor init sequence */
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U8X8_CA(0xdb, 0x30), /* VCOMH Deselect Level */
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U8X8_CA(0xd3, 0x0e), /* CS1 */
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// U8X8_CA(0xd3, 0x92), /* CS2 */
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U8X8_CA(0xd3, 39), /* display offset */
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U8X8_CA(0xda, 0x12), /* Set SEG Pins Hardware Configuration: */
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U8X8_CA(0x81, 0x6b), /* contrast */
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//U8X8_CA(0xd9, 0x22), /* Set Phase Length */
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//U8X8_CA(0xdb, 0x30), /* VCOMH Deselect Level */
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//U8X8_CA(0xad, 0x10), /* Internal IREF Enable */
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U8X8_CA(0x81, 0x70), /* contrast */
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U8X8_CA(0x20, 0x00), /* Memory Addressing Mode: Horizontal */
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//U8X8_CA(0x8d, 0x01), /* unknown in SSD1320 datasheet, disable internal charge pump 1 */
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//U8X8_CA(0xac, 0x00), /* unknown in SSD1320 datasheet, disable internal charge pump 2 */
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U8X8_C(0xa4), /* display RAM on */
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U8X8_C(0xa6), /* normal display */
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@ -701,11 +689,14 @@ static const uint8_t u8x8_d_ssd1320_160x80_init_seq[] = {
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uint8_t u8x8_d_ssd1320_160x80(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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{
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if ( u8x8_d_ssd1320_common_2(u8x8, msg, arg_int, arg_ptr) != 0 )
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return 1;
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switch(msg)
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{
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case U8X8_MSG_DISPLAY_SETUP_MEMORY:
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u8x8_d_helper_display_setup_memory(u8x8, &u8x8_d_ssd1320_160x80_display_info);
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break;
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case U8X8_MSG_DISPLAY_INIT:
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@ -725,7 +716,7 @@ uint8_t u8x8_d_ssd1320_160x80(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *
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break;
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default:
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return u8x8_d_ssd1320_common_2(u8x8, msg, arg_int, arg_ptr);
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break;
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}
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return 1;
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}
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@ -371,7 +371,7 @@ void loop(void) {
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u8g2.firstPage();
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do {
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u8g2.setFont(u8g2_font_ncenB10_tr);
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u8g2.drawStr(0,54,"Hello World!");
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u8g2.drawStr(0,24,"Hello World!");
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} while ( u8g2.nextPage() );
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//delay(1000);
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}
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@ -154,7 +154,7 @@
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//U8G2_SSD1320_160X132_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_SSD1320_160X132_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_SSD1320_160X80_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_SSD1320_160X80_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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U8G2_SSD1320_160X80_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);
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//U8G2_LD7032_60X32_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 11, /* data=*/ 12, /* cs=*/ 9, /* dc=*/ 10, /* reset=*/ 8); // SW SPI Nano Board
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//U8G2_LD7032_60X32_1_4W_SW_I2C u8g2(U8G2_R0, /* clock=*/ 11, /* data=*/ 12, /* reset=*/ U8X8_PIN_NONE); // NOT TESTED!
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//U8G2_LD7032_60X32_ALT_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 11, /* data=*/ 12, /* cs=*/ 9, /* dc=*/ 10, /* reset=*/ 8); // SW SPI Nano Board
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@ -1,2 +1,2 @@
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# without 'v' prefix
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echo -n "2.33.1"
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echo -n "2.33.2"
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