diff --git a/csrc/u8x8_d_ssd1322.c b/csrc/u8x8_d_ssd1322.c index 3f045346..b39ec267 100644 --- a/csrc/u8x8_d_ssd1322.c +++ b/csrc/u8x8_d_ssd1322.c @@ -427,6 +427,127 @@ uint8_t u8x8_d_ssd1322_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void return 1; } + + +/*=========================================================*/ +/* + + Top Win OLED 240x128 + + Discussion: https://github.com/olikraus/u8g2/discussions/2308 + Issue: https://github.com/olikraus/u8g2/issues/2310 + + The main difference to the previous device seems to be the dual com line mode + (0x0a0 command) + +*/ + +static const uint8_t u8x8_d_ssd1322_topwin_240x128_flip0_seq[] = { + U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ + U8X8_CAA(0x0a0, 0x036, 0x001), /* remap */ + U8X8_END_TRANSFER(), /* disable chip */ + U8X8_END() /* end of sequence */ +}; + +static const uint8_t u8x8_d_ssd1322_topwin_240x128_flip1_seq[] = { + U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ + U8X8_CAA(0x0a0, 0x024, 0x001), /* remap */ + U8X8_END_TRANSFER(), /* disable chip */ + U8X8_END() /* end of sequence */ +}; + + +static const u8x8_display_info_t u8x8_ssd1322_topwin_240x128_display_info = +{ + /* chip_enable_level = */ 0, + /* chip_disable_level = */ 1, + + /* post_chip_enable_wait_ns = */ 20, + /* pre_chip_disable_wait_ns = */ 10, + /* reset_pulse_width_ms = */ 100, /* SSD1322: 2 us */ + /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */ + /* sda_setup_time_ns = */ 50, /* SSD1322: 15ns, but cycle time is 100ns, so use 100/2 */ + /* sck_pulse_width_ns = */ 50, /* SSD1322: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */ + /* sck_clock_hz = */ 10000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215), 10 MHz (issue 301) */ + /* spi_mode = */ 0, /* active high, rising edge */ + /* i2c_bus_clock_100kHz = */ 4, + /* data_setup_time_ns = */ 10, + /* write_pulse_width_ns = */ 150, /* SSD1322: cycle time is 300ns, so use 300/2 = 150 */ + /* tile_width = */ 30, /* 240 pixel, so we require 30 bytes for this */ + /* tile_height = */ 16, + /* default_x_offset = */ 24, /* this is the byte offset (there are two pixel per byte with 4 bit per pixel) */ + /* flipmode_x_offset = */ 0x000, + /* pixel_width = */ 240, + /* pixel_height = */ 128 +}; + + +static const uint8_t u8x8_d_ssd1322_topwin_240x128_init_seq[] = { + + U8X8_DLY(1), + U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */ + U8X8_DLY(1), + + U8X8_CA(0xfd, 0x12), /* unlock */ + U8X8_C(0xae), /* display off */ + U8X8_CA(0xb3, 0x91), /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */ + U8X8_CA(0xca, 0x7f), /* multiplex ratio 1/128 Duty (0x0F~0x7F) */ + U8X8_CA(0xa2, 0x00), /* display offset, shift mapping ram counter */ + U8X8_CA(0xa1, 0x00), /* display start line */ + U8X8_CAA(0xa0, 0x36, 0x001), /* Set Re-Map / Dual COM Line Mode, https://github.com/olikraus/u8g2/discussions/2308 */ + U8X8_CA(0xab, 0x01), /* Enable Internal VDD Regulator */ + U8X8_CAA(0xb4, 0xa0, 0x005|0x0fd), /* Display Enhancement A */ + U8X8_CA(0xc1, 0x9f), /* contrast */ + U8X8_CA(0xc7, 0x0f), /* Set Scale Factor of Segment Output Current Control */ + U8X8_C(0xb9), /* linear grayscale */ + U8X8_CA(0xb1, 0xe2), /* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */ + U8X8_CAA(0xd1, 0x082|0x020, 0x020), /* Display Enhancement B */ + U8X8_CA(0xbb, 0x1f), /* precharge voltage */ + U8X8_CA(0xb6, 0x08), /* precharge period */ + U8X8_CA(0xbe, 0x07), /* vcomh */ + U8X8_C(0xa6), /* normal display */ + U8X8_C(0xa9), /* exit partial display */ + + + U8X8_DLY(1), /* delay 2ms */ + + + U8X8_END_TRANSFER(), /* disable chip */ + U8X8_END() /* end of sequence */ +}; + + +uint8_t u8x8_d_ssd1322_topwin_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr) +{ + switch(msg) + { + case U8X8_MSG_DISPLAY_SETUP_MEMORY: + u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1322_topwin_240x128_display_info); + break; + case U8X8_MSG_DISPLAY_INIT: + u8x8_d_helper_display_init(u8x8); + u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_topwin_240x128_init_seq); + break; + case U8X8_MSG_DISPLAY_SET_FLIP_MODE: + if ( arg_int == 0 ) + { + u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_topwin_240x128_flip0_seq); + u8x8->x_offset = u8x8->display_info->default_x_offset; + } + else + { + u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_topwin_240x128_flip1_seq); + u8x8->x_offset = u8x8->display_info->flipmode_x_offset; + } + break; + + default: + return u8x8_d_ssd1322_common(u8x8, msg, arg_int, arg_ptr); + } + return 1; +} + + /*=========================================================*/ /* NHD-2.7-12864WDW3-M diff --git a/tools/codebuild/codebuild.c b/tools/codebuild/codebuild.c index 43d8105d..f74f032d 100644 --- a/tools/codebuild/codebuild.c +++ b/tools/codebuild/codebuild.c @@ -2032,6 +2032,7 @@ struct controller controller_list[] = "", /* is_generate_u8g2_class= */ 1, { { "240x128" }, + { "topwin_240x128" }, { NULL } } }, diff --git a/tools/inoupdate/frame_buffer.ino b/tools/inoupdate/frame_buffer.ino index 5c71f686..969168a4 100644 --- a/tools/inoupdate/frame_buffer.ino +++ b/tools/inoupdate/frame_buffer.ino @@ -59,6 +59,7 @@ //U8G2_SSD1320_160X80_F_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); //U8G2_SSD1320_160X80_F_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); //U8G2_SSD1322_240x128_F_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); // Enable U8G2_16BIT in u8g2.h +//U8G2_SSD1322_TOPWIN_240x128_F_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); // Enable U8G2_16BIT in u8g2.h //U8G2_SSD1322_NHD_256X64_F_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); // Enable U8G2_16BIT in u8g2.h //U8G2_SSD1322_NHD_256X64_F_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); // Enable U8G2_16BIT in u8g2.h //U8G2_SSD1362_256X64_F_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); // Enable U8G2_16BIT in u8g2.h diff --git a/tools/inoupdate/page_buffer.ino b/tools/inoupdate/page_buffer.ino index ad5d7eb2..7b4320b4 100644 --- a/tools/inoupdate/page_buffer.ino +++ b/tools/inoupdate/page_buffer.ino @@ -55,6 +55,7 @@ //U8G2_SSD1306_96X40_1_HW_I2C u8g2(U8G2_R0, /* reset=*/ U8X8_PIN_NONE); //U8G2_SSD1306_96X39_1_HW_I2C u8g2(U8G2_R0, /* reset=*/ U8X8_PIN_NONE); //U8G2_SSD1322_240X128_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); +//U8G2_SSD1322_TOPWIN_240X128_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); //U8G2_SSD1322_NHD_256X64_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); // Enable U8G2_16BIT in u8g2.h //U8G2_SSD1322_NHD_256X64_1_4W_HW_SPI u8g2(U8G2_R0, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); // Enable U8G2_16BIT in u8g2.h //U8G2_SSD1362_256X64_1_4W_SW_SPI u8g2(U8G2_R0, /* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); // Enable U8G2_16BIT in u8g2.h diff --git a/tools/inoupdate/u8x8.ino b/tools/inoupdate/u8x8.ino index 66288493..e1a78e0b 100644 --- a/tools/inoupdate/u8x8.ino +++ b/tools/inoupdate/u8x8.ino @@ -66,6 +66,7 @@ //U8X8_SSD1320_160X80_4W_SW_SPI u8x8(/* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); //U8X8_SSD1320_160X80_4W_HW_SPI u8x8(/* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); //U8X8_SSD1322_240X128_4W_SW_SPI u8x8(/* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); +//U8X8_SSD1322_TOPWIN_240X128_4W_SW_SPI u8x8(/* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); //U8X8_SSD1322_NHD_256X64_4W_SW_SPI u8x8(/* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); //U8X8_SSD1322_NHD_256X64_4W_HW_SPI u8x8(/* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8); //U8X8_SSD1362_256X64_4W_SW_SPI u8x8(/* clock=*/ 13, /* data=*/ 11, /* cs=*/ 10, /* dc=*/ 9, /* reset=*/ 8);