started with ssd1322
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olikraus
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/*
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u8x8_d_ssd1322.c
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Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)
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Copyright (c) 2016, olikraus@gmail.com
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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The ssd1322 controller does not support hardware graphics flip.
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Contrast adjustment is done by an external resistor --> no support for contrast adjustment
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*/
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#include "u8x8.h"
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static const uint8_t u8x8_d_ssd1322_init_seq[] = {
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U8X8_DLY(100),
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_DLY(100),
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U8X8_CA(0xfd, 0x12), /* unlock */
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U8X8_C(0xae), /* display off */
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U8X8_CA(0xb3, 0x91), /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
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U8X8_CA(0xca, 0x3f), /* multiplex ratio 1/64 Duty (0x0F~0x3F) */
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U8X8_CA(0xa2, 0x00), /* display offset, shift mapping ram counter */
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U8X8_CA(0xa1, 0x00), /* display start line */
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U8X8_CAA(0xa0, 0x14, 0x11), /* Set Re-Map / Dual COM Line Mode */
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U8X8_CA(0xab, 0x01), /* Enable Internal VDD Regulator */
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U8X8_CAA(0xb4, 0xa0, 0x005|0x0fd), /* Display Enhancement A */
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U8X8_CA(0xc1, 0x9f), /* contrast */
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U8X8_CA(0xc7, 0x0f), /* Set Scale Factor of Segment Output Current Control */
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U8X8_C(0xb9), /* linear grayscale */
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U8X8_CA(0xb1, 0xe2), /* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */
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U8X8_CAA(0xd1, 0x082|0x020, 0x020), /* Display Enhancement B */
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U8X8_DLY(2), /* delay 2ms */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1322_powersave0_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0x0af), /* ssd1322: display on */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1322_powersave1_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0x0ae), /* ssd1322: display off */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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uint8_t u8x8_d_ssd1322_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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{
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uint8_t x, y, c, i;
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uint8_t *ptr;
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switch(msg)
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{
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/* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */
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/*
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case U8X8_MSG_DISPLAY_SETUP_MEMORY:
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break;
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*/
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case U8X8_MSG_DISPLAY_INIT:
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u8x8_d_helper_display_init(u8x8);
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_init_seq);
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break;
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case U8X8_MSG_DISPLAY_SET_POWER_SAVE:
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if ( arg_int == 0 )
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_powersave0_seq);
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else
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_powersave1_seq);
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break;
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case U8X8_MSG_DISPLAY_DRAW_TILE:
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y = (((u8x8_tile_t *)arg_ptr)->y_pos);
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y*=8;
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x = ((u8x8_tile_t *)arg_ptr)->x_pos;
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x /= 2; /* not sure whether this is a clever idea, problem is, the ssd1322 can address only every second tile */
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if ( y >= 32 ) /* this is the adjustment for 128x64 displays */
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{
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y-=32;
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x+=8;
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}
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u8x8_cad_StartTransfer(u8x8);
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/*
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Tile structure is reused here for the ssd1322, however u8x8 is not supported
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tile_ptr points to data which has cnt*8 bytes (same as SSD1306 tiles)
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Buffer is expected to have 8 lines of code fitting to the ssd1322 internal memory
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"cnt" includes the number of horizontal bytes. width is equal to cnt*8
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Also important: Width must be a multiple of 16 (ssd1322 requirement), so cnt must be even.
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TODO: Consider arg_int, however arg_int is not used by u8g2
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*/
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c = ((u8x8_tile_t *)arg_ptr)->cnt; /* number of tiles */
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ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr; /* data ptr to the tiles */
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for( i = 0; i < 8; i++ )
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{
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u8x8_cad_SendCmd(u8x8, 0x03e ); /* enable extended mode */
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u8x8_cad_SendCmd(u8x8, 0x080 | (y+i) ); /* y pos */
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u8x8_cad_SendCmd(u8x8, 0x080 | x ); /* set x pos */
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c = ((u8x8_tile_t *)arg_ptr)->cnt; /* number of tiles */
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u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, 200, NULL); /* extra dely required */
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u8x8_cad_SendData(u8x8, c, ptr); /* note: SendData can not handle more than 255 bytes, send one line of data */
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ptr += c;
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u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, 200, NULL); /* extra dely required */
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}
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u8x8_cad_EndTransfer(u8x8);
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break;
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default:
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return 0;
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}
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return 1;
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}
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static const u8x8_display_info_t u8x8_ssd1322_192x32_display_info =
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{
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/* chip_enable_level = */ 1,
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/* chip_disable_level = */ 0,
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/* post_chip_enable_wait_ns = */ 5,
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/* pre_chip_disable_wait_ns = */ 5,
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/* reset_pulse_width_ms = */ 1,
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/* post_reset_wait_ms = */ 6,
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/* sda_setup_time_ns = */ 20,
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/* sck_pulse_width_ns = */ 140, /* datasheet ssd1322 */
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/* sck_takeover_edge = */ 1, /* rising edge */
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/* i2c_bus_clock_100kHz = */ 4,
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/* data_setup_time_ns = */ 30,
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/* write_pulse_width_ns = */ 40,
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/* tile_width = */ 24,
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/* tile_hight = */ 4,
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/* default_x_offset = */ 0,
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/* flipmode_x_offset = */ 0,
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/* pixel_width = */ 192,
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/* pixel_height = */ 32
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};
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static const u8x8_display_info_t u8x8_ssd1322_128x64_display_info =
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{
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/* chip_enable_level = */ 1,
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/* chip_disable_level = */ 0,
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/* post_chip_enable_wait_ns = */ 5,
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/* pre_chip_disable_wait_ns = */ 5,
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/* reset_pulse_width_ms = */ 1,
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/* post_reset_wait_ms = */ 6,
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/* sda_setup_time_ns = */ 20,
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/* sck_pulse_width_ns = */ 140, /* */
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/* sck_takeover_edge = */ 1, /* rising edge */
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/* i2c_bus_clock_100kHz = */ 4,
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/* data_setup_time_ns = */ 30,
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/* write_pulse_width_ns = */ 40,
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/* tile_width = */ 16,
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/* tile_hight = */ 8,
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/* default_x_offset = */ 0,
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/* flipmode_x_offset = */ 0,
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/* pixel_width = */ 128,
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/* pixel_height = */ 64
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};
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uint8_t u8x8_d_ssd1322_192x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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{
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switch(msg)
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{
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case U8X8_MSG_DISPLAY_SETUP_MEMORY:
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u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1322_192x32_display_info);
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break;
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default:
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return u8x8_d_ssd1322_common(u8x8, msg, arg_int, arg_ptr);
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}
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return 1;
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}
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uint8_t u8x8_d_ssd1322_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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{
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switch(msg)
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{
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case U8X8_MSG_DISPLAY_SETUP_MEMORY:
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u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1322_128x64_display_info);
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break;
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default:
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return u8x8_d_ssd1322_common(u8x8, msg, arg_int, arg_ptr);
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}
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return 1;
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}
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