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RTC

This commit is contained in:
olikraus 2017-04-11 22:11:47 +02:00
parent f081db6405
commit 286894e404
1 changed files with 45 additions and 0 deletions
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45
sys/arm/stm32l031x6/rtc_test/main.c
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@ -104,11 +104,56 @@ int main()
display_Write(" Hz\n");
/* real time clock enable */
RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR */
/* externel 32K clock source */
RCC->CSR |= RCC_CSR_LSEBYP; /* bypass oscillator */
/* externel 32K oscillator */
//RCC->CSR &= ~RCC_CSR_LSEBYP; /* no bypass oscillator */
//RCC->CSR &= ~RCC_CSR_LSEDRV_Msk /* lowest drive */
//RCC->CSR |= RCC_CSR_LSEDRV_0; /* medium low drive */
RCC->CSR |= RCC_CSR_LSEON; /* enable low speed external clock */
delay_micro_seconds(100000*5); /* LSE requires between 100ms to 200ms */
if ( RCC->CSR & RCC_CSR_LSERDY )
display_Write("32K Clock Ready\n");
else
display_Write("32K Clock Error\n");
RCC->CSR &= ~RCC_CSR_RTCSEL_Msk; /* no clock selection for RTC */
RCC->CSR |= RCC_CSR_RTCSEL_LSE; /* select LSE */
RCC->CSR |= RCC_CSR_RTCEN; /* enable RTC */
RTC->WPR = 0x0ca; /* disable RTC write protection */
RTC->WPR = 0x053;
RTC->ISR = RTC_ISR_INIT; /* request RTC stop */
while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF) /* wait for stop */
;
RTC->PRER = 0x07f00ff;
RTC->TR = 0;
RTC->ISR =~ RTC_ISR_INIT; /* start RTC */
RTC->WPR = 0; /* enable RTC write protection */
RTC->WPR = 0;
//PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR */
for(;;)
{
delay_micro_seconds(500000);
GPIOA->BSRR = GPIO_BSRR_BS_13; /* atomic set PA13 */
delay_micro_seconds(500000);
GPIOA->BSRR = GPIO_BSRR_BR_13; /* atomic clr PA13 */
display_WriteUnsigned(RTC->TR);
display_Write("\n");
}
}