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issue #347, LUT transfer during refresh

This commit is contained in:
olikraus 2017-09-08 09:10:30 +02:00
parent 60e7876941
commit 0cf990e4f8
1 changed files with 48 additions and 0 deletions
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48
csrc/u8x8_d_il3820_296x128.c
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@ -494,6 +494,54 @@ static const uint8_t u8x8_d_il3820_to_display_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
/*
0x50, 0xAA, 0x55, 0xAA, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xFF, 0xFF, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
measured 1582 ms
*/
U8X8_C(0x32), /* write LUT register*/
/* original values */
U8X8_A(0x50),
U8X8_A(0xaa),
U8X8_A(0x55),
U8X8_A(0xaa),
U8X8_A(0x11),
U8X8_A(0x11),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
/* Timing part of the LUT, 20 Phases with 4 bit each: 10 bytes */
U8X8_A(0xff),
U8X8_A(0xff),
U8X8_A(0x3f),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_A(0x00),
U8X8_CA(0x22, 0xc4), /* display update seq. option: clk -> CP -> LUT -> initial display -> pattern display */
U8X8_C(0x20), /* execute sequence */