88 lines
1.8 KiB
C
88 lines
1.8 KiB
C
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#ifndef LPC8XX_CTIMER_H_
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#define LPC8XX_CTIMER_H_
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// Interrupt Register (IR) shifters
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#define MR0INT 0
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#define MR1INT 1
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#define MR2INT 2
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#define MR3INT 3
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#define CR0INT 4
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#define CR1INT 5
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#define CR2INT 6
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#define CR3INT 7
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// Timer Control Register (TCR) shifters
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#define CEN 0
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#define CRST 1
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// Match Control Register (MCR) shifters
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#define MR0I 0
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#define MR0R 1
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#define MR0S 2
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#define MR1I 3
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#define MR1R 4
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#define MR1S 5
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#define MR2I 6
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#define MR2R 7
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#define MR2S 8
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#define MR3I 9
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#define MR3R 10
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#define MR3S 11
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// Capture Control Register (CCR) shifters
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#define CAP0RE 0
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#define CAP0FE 1
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#define CAP0I 2
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#define CAP1RE 3
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#define CAP1FE 4
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#define CAP1I 5
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#define CAP2RE 6
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#define CAP2FE 7
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#define CAP2I 8
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#define CAP3RE 9
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#define CAP3FE 10
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#define CAP3I 11
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// External Match Register (EMR) shifters
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#define EM0 0
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#define EM1 1
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#define EM2 2
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#define EM3 3
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#define EMC0 4
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#define EMC1 6
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#define EMC2 8
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#define EMC3 10
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// EMR bit fields
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#define DO_NOTHING_ON_MATCH 0x0
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#define CLEAR_ON_MATCH 0x1
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#define SET_ON_MATCH 0x2
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#define TOGGLE_ON_MATCH 0x3
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// Count Control Register (CTCR) shifters
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#define CTMODE 0
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#define CINSEL 2
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#define ENCC 4
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#define SELCC 5
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// CTCR bit fields
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#define TIMER_MODE 0x0
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#define COUNTER_MODE_RISING 0x1
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#define COUNTER_MODE_FALLING 0x2
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#define COUNTER_MODE_BOTH 0x3
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#define CLEAR_ON_CAP0_RISING 0x0
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#define CLEAR_ON_CAP0_FALLING 0x1
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#define CLEAR_ON_CAP1_RISING 0x2
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#define CLEAR_ON_CAP1_FALLING 0x3
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#define CLEAR_ON_CAP2_RISING 0x4
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#define CLEAR_ON_CAP2_FALLING 0x5
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#define CLEAR_ON_CAP3_RISING 0x6
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#define CLEAR_ON_CAP3_FALLING 0x7
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// PWM Control Register (PWMC) shifters
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#define PWMEN0 0
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#define PWMEN1 1
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#define PWMEN2 2
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#define PWMEN3 3
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#endif // LPC8XX_CTIMER_H_
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